Ing. Jiri KADLEC CSc.
Department of Signal Processing, UTIA, CAS
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Current position: | Head of the Department of Signal Processing | ||||||||||
Research interests: | recursive system identification algorithms suitable for FPGA; rapid prototyping of advanced signal processing algorithms; scalable floating point arithmetic for FPGA SoC designs | ||||||||||
Current R&D projects: | SOIL, StorAIge, EECONE, Listen2Future | ||||||||||
Past EU R&D projects: | Arrowhead Tools, FitOptiVis, WAKeMeUP, Productive4.0, SILENSE, THINGS2DO, PANACHE, EMC2, ALMARVI, IDEAS, AETHER, RECONF 2, HSLA | ||||||||||
Past national R&D projects: | CAK and CAK 2, VLAM, SESAP | ||||||||||
Past support projects: | Idealist2014, Idealist2011, COSINE 2, Idealist7fp, COSINE, IST World, Idealist34, Idealist-5fp, Idealist-East, NetCeE, CEeB | ||||||||||
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Selected publications: |
Coleman J. N., Softley C. I., Kadlec J., Matousek R., Tichy M., Pohl Z., Benschop N. F.:
The European Logarithmic Microprocessor. Kadlec J., Schier J.:
Analysis of a normalized QR filter using Bayesian description of propagated data. Coleman J. N., Chester E. I., Softley C. I., Kadlec J.:
Arithmetic on the European Logarithmic Microprocessor. Kadlec J., Chappel S.:
Implementing floating-point DSP. |
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