HSLAThe first phase of this project has demonstrated that LNS arithmetic will offer a substantial speed advantage over existing floating-point devices. In all cases its accuracy is also either equivalent to or better than floating-point, and its complexity is similar. It is the objective of the second phase to bring the LNS hardware system into commercial use, and thereby to enhance the competitiveness of European digital electronics. Specific objectives are as follows:
- To design LNS arithmetic cells, a LNS-based microprocessor, and development board
- To provide a practical demonstration that the LNS-based device is faster than floating-point, and as accurate and no more complex
- To provide a practical demonstration that a LNS-based ASIC device offers superior accuracy to an equivalent fixed-point device, at around the same speed, and to show where this is of benefit
- To carry out further smaller demonstrations of practical applications running on the development board
- To undertake further proof of the system at independent test sites, and hence to gain commercial acceptance
- To continue development of the arithmetic unit and also of fixed-point arithmetic techniques
European Logarithmic Microprocessor in SiliconThe first LNS-based microprocessor - European Logarithmic Microprocessor (ELM) - has been manufactured in CMOS 0.18 micron technology at Philips NatLab in Eindhoven, NL. The ELM is designed to offer convenient access to, and efficient utilisation of, a LNS arithmetic unit. Suitable application areas include digital signal procesing, digital control, graphics, and numerical analysis. Technical details can befound in an ELM brief.
HSLA version 3.0.0 evaluation CD-ROM packageOne of the results of the HSLA project is an FPGA implementation of the Logarithmic Arithmetic Unit (LNS ALU). We decided to provide a small package containing all the needed files to test our type of arithmetic in your applications.
FPL 2002 PresentationsThe results of the HSLA project will be presented at the 12th International Conference on Field Programmable Logic and Applications (FPL 2002) in Montpelier, France. The presentation will include 1 paper, 3 posters and running demo.
Please, do not hesitate to contact Jiri Kadlec to obtain more information.
|Name:||A High Speed Logarithmic Arithmetic|
|Project No.:|| ESPRIT 23544 (Phase I)|
ESPRIT 33544 (Phase II)
|Consortium:||University of Newcastle upon Tyne, Dept. Electrical and Electronic Engineering, UK|
University College Dublin, DSP Group, Ireland
Philips Research Eindhoven, Holland
Institute of Information Theory and Automation of the CAS
Massana Ltd., Dublin, Ireland
|Duration:||January 1999 - July 2002|
- Logarithmic (dual) ALU Core
- Logaritmická (dvojitá) aritmetická jednotka
- Adaptive Recursive Least Squares Lattice Filter
- Adaptivní Lattice filtr
- Lattice IP Core used in Real-time Lattice Demo on XESS Board
- RLS Lattice Macros for Virtex/E/Virtex2 with LNS ALU 19/32-bit
- Adaptive Recursive Least Square Lattice Filter
- Logarithmic Dual Pipelined ALU Macros 19-bit and 32-bit
- Matlab Toolbox for High-Level Bit-Exact Emulation of FPGA Designs
- Pipelined Implementations of the a Priori Error-Feedback LSL Algorithm Using Logarithmic Arithmetic
- Logarithmic Arithmetic Core Based RLS Lattice Implementation
- European Logarithmic Microprocessor
- Floating-Point Like Arithmetic for FPGA