Ing. Jiri KADLEC CSc.

Department of Signal Processing, UTIA, CAS
Pod Vodarenskou vezi 1143/4
182 00 Praha 8
Czech Republic

phone:	+420/266 052 216
email:

Current position:

Head of the Department of Signal Processing

Research interests:

recursive system identification algorithms suitable for FPGA; rapid prototyping of advanced signal processing algorithms; scalable floating point arithmetic for FPGA SoC designs

Current R&D projects:

SOIL, StorAIge, EECONE, Listen2Future

Past EU R&D projects:

Arrowhead Tools, FitOptiVis, WAKeMeUP, Productive4.0, SILENSE, THINGS2DO, PANACHE, EMC2, ALMARVI, IDEAS, AETHER, RECONF 2, HSLA

Past national R&D projects:

CAK and CAK 2, VLAM, SESAP

Past support projects:

Idealist2014, Idealist2011, COSINE 2, Idealist7fp, COSINE, IST World, Idealist34, Idealist-5fp, Idealist-East, NetCeE, CEeB

Positions:

since 2000	Senior researcher and head of the Department of Signal Processing
1990-2000	Researcher (Dept. of Adaptive Systems in UTIA)

Qualification:

1987	CSc. (similar to Ph.D.) from the CAS (fast, normalised algorithms for identification of adaptive systems)
1982	graduated Ing. (similar to MSc.) in technical cybernetics and automation from the CTU Prague

Professional activities:

2014-2020	Member of HORIZON 2020 ICT Committee
2007-2013	Member of ICT Committee for 7^th Framework Programme EU
2002-2006	Member of ICT Committee for 6^th Framework Programme EU
1998-2002	Member of IST Committee for 5^th Framework Programme EU
since 2005	Member of REI ("Council for support of AS CR Participation in European Integration of Research and Development")

Long-term visits:

1995-1996	Katholieke Universiteit Leuven, Belgium (6 months)
1992-1995	Queen's University of Belfast, UK
1990	University of Athens, Dep. of Physics (Humboldt Research Fellowship, 4 months)
1989	Ruhr University Bochum (Humboldt Research Fellowship, 1 year)

Selected publications:

Coleman J. N., Softley C. I., Kadlec J., Matousek R., Tichy M., Pohl Z., Benschop N. F.: The European Logarithmic Microprocessor.
IEEE Transactions on Computers, 57 (2008), 4, 532-546.

Kadlec J., Schier J.: Analysis of a normalized QR filter using Bayesian description of propagated data.
International Journal of Adaptive Control and Signal Processing, 13 (1999), 6, 487-505.

Coleman J. N., Chester E. I., Softley C. I., Kadlec J.: Arithmetic on the European Logarithmic Microprocessor.
IEEE Transactions on Computers, 49 (2000), 7, 702-715.

Kadlec J., Chappel S.: Implementing floating-point DSP.
Embedded Magazine, 2 (2006), 3, 12-14.