Ing. Zdenek POHL, Ph.D

Department of Signal Processing, UTIA, CAS
Pod Vodarenskou vezi 1143/4
182 00 Praha 8
Czech Republic

phone:	+420/266 052 212
email:

Current position:

Deputy head of the Department of Signal Processing

Research interests:

Informatics and programmable logic; parallel and extremely fast system-identification algorithms; FPGA implementations

Current R&D projects:

Listen2Future, StorAIge

Past EU R&D projects:

Arrowhead Tools FitOptiVis, WAKeMeUP, Productive4.0, SILENSE, PANACHE, THINGS2DO, ALMARVI, EMC2, SCALOPES, AETHER, RECONF 2, HSLA

Past national R&D projects:

ADAS, SURF, RIPAC, VLAM, SESAP, CAK and CAK 2

Qualification:

2008	Ph.D. in control engineering from the Faculty of Electrical Engineering, CTU in Prague
since 2001	Member of the Signal Processing group
2001	graduated from FEE CTU Prague

Selected publications:

Pohl Z., Schier J., Licko M., Hermanek A., Tichy M.: Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping.
In: Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003. (Werner B. ed.). IEEE Computer Society Press, Los Alamitos 2003, pp. 1-6

Danek M., Pohl Z., Nasi K., Karoubalis T.: Figaro - an automatic tool flow for designs with dynamic reconfiguration.
In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005. (Rissa T., Wilton S., Leong P. eds.). Academy of Finland, Tampere 2005, pp. 590-593.

Pohl Z., Kadlec J., Sucha P., Hanzalek Z.: Performance tuning of iterative algorithms in signal processing.
In: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005. (Rissa T., Wilton S., Leong P. eds.). Academy of Finland, Tampere 2005, pp. 699-702.