Tool for Preparation of Emulation of Time-Annotated ASIC Netlists
Description
This package contains the SDFAn tool. This tool is part of the design flow for emulation of time-annotated ASIC netlists using FPGA that was developed within the RETAC project. The tool processes a circuit netlist and SDF file and creates a modified netlist that is used for emulation in an FPGA.
Package Summary
| Title |
Tool for Preparation of Emulation of Time-annotated ASIC Netlists |
| Filename |
sdfan.zip |
| License |
Freeware |
| Package content |
ZIP archive with the SDFAn tool and an example |
| Size |
1 617 040 Bytes |
Required tools
& platform |
The SDFAn tool is an executable file for Windows. No additional tools are required. |
Result Category
Please, do not hesitate to contact
Jiri Kadlec to obtain more information.
