PF2006
We would like to wish all our friends, colleagues, supporters, and symphatizers a peaceful Christmas and a lot of good luck in the coming year 2006. PS. See our first baked chip.
SoC 2005 IEEE Symposium on System-on-Chip, Tampere, Suomi
We will visit the International Symposium on System-on-Chip in Tapmere to see contemporary methods in System on Chip and Network on Chip.SiPS 2005 IEEE Workshop starts next week
Next week we will present our paper Optimization of Finite Interval CMA Implementation for FPGA, co-authored by our group and the folks from the Department of Control Engineering, Czech Technical University in Prague, at Signal Processing Systems Workshop SiPS 2005. So see you in Athens.UTIA in The Syndicated
The Synplicity's newsletter published our article "Reconfigurable System-on-a-Chip". For details see Volume 5, Issue 2.FPL2005 Conference
Our group will present two posters at the FPL conference in Tampere, Finland (Aug. 23-26, 2005). The first poster describes an automatic tool flow for dynamic reconfiguration of FPGAs, the second poster shows a technique for tuning of iterative DSP algorithms implemented in FPGAs.SiPS 2005 IEEE Workshop on Signal Processing
A paper Optimization of Finite Interval CMA Implementation for FPGA, co-authored by our group and the folks from the Department of Control Engineering, Czech Technical University in Prague, has been accepted for presentation at the SiPS 2005 Workshop on Signal Processing in Athens, Greece.Students from ISEP in our department
A group of students from ISEP (Institut Sup�ieur d'Electronique de Paris) is visiting our department in July for professional training.16th IFAC World Congress
We will present our current research projects at the 16th IFAC World Congress held in Prague on July 4-8. Visit us at the Idealist & UTIA booth.UTIA in EE Times
A press release published in EE Times mentions UTIA research.UTIA in Press
Two press releases that mention the research done in UTIA used by our industrial partners: Celoxica and Embedded.com.UTIA Cooperates with ERA
ERA and UTIA announced an ongoing cooperation on FPGA implementations of advanced DSP algorithms for novel passive radar systems. More information can be found in the press release.Atmel Application Journal
The Atmel Application Journal reprints our DDECS2004 paper on the extended FPSLIC platform. For more information see the article "Reconfigurable System on a Programmable Chip Platform" in AAJ Number 4 (Spring 2005).Reconfigurable Scrolling Demo
Our application note "Performing Dynamic Reconfiguration in FPSLIC Devices - A Scrolling Message Display" got published on the Atmel web page. The application note describes on a simple example the principles of dynamic reconfiguration with the FPSLIC device and the new version of the System Designer/Figaro tools.FPGA2005 Symposium
Our group will present three posters at the FPGA2005 symposium in Monterey, CA USA (Feb. 20-22, 2005): VHDL-level automatic partitioning, an extended version of the Atmel Figaro tool with a support for dynamic reconfiguration, and experiments with dynamic reconfiguration in Atmel FPSLIC and Xilinx VIRTEX. We would like to thank Atmel and Xilinx for the continuous support of this work.EDN Magazine
The Electronic Design News magazine refers about the work done by our research group on dynamic reconfiguration. For more information see the article in the 2004/11/11 issue.Notebook for Blind Users GIN
Institute of Information Theory and Automation, AS CR and Press Center of AS CR would like to invite you to a press conference "Notebook for Blind Users GIN - New Series Presentation" that will take place in the building of the Academy of Sciences CR (Národní 3, Praha 1, room 108) on December 6th 2004 at 10am. A full press release in Czech language is available at the web portal of Press Center of AS CR.Meeting with Mrs Rosalie Zobel in UTIA 25. Nov. 2004
OKO IST organized a working meeting with Mrs. Rosalie Zobel and Mr. Stephan Pascall from the European Commission. Mrs Zobel is a head of IST Programme Directorate C Miniaturisation, Embedded Systems, Societal Applications and Mr. Pascall is an advisor. The invited Czech participants had the opportunity to discuss their ideas linked to comming IST Calls for proposers and to 7th Framework Programme.FPL2004 Conference
Our group presented at the FPL 2004 exhibition in Antwerp, Belgium (Aug. 30 - Sept. 1, 2004). Visit our virtual booth.Workshop FET - Future and Emerging Technologies projects in the frame of IST FP6
Our group (OKO IST and IDEALIST) organized a workshop FET - Future and Emerging Technologies projects in the frame of IST FP6, 14 May 2004 in Prague. Main speakers: Thierry Van der Pyl (FET Proactive Initiatives); Gustav Kalbe (FET Open Domain). Participants had the opportunity to get actual information about FET projects and to discuss their proposals individually with Brussels representatives. You can download the PRESENTATION from this workshop (.pdf 728 kB).FPGA2004 Symposium
Our group will present a poster at the FPGA2004 symposium in Monterey, CA USA (Feb. 22-24, 2004). The poster presents a metric based on a graph theory that can be used for assessing FPGA routing models with different levels of abstraction. The metric has been tested on a wire-type routing model and a global routing model of Xilinx XC4000 FPGAs.Cooperation with Celoxica
Some demos developed in our Department has been published at the Community Contributions web page of Celoxica, Ltd. These include Simulink testbench for evaluation of the Celoxica floating point library, active noise cancellation with adaptive RLS Lattice algorithm, and logarithmic ALU. You can also see our research papers published at the University Program pages of CeloxicaBaiona Workshop on Signal Processing in Communications
Our group will present a poster on Using logarithmic arithmetic for FPGA implementation of the Givens rotations at the Baiona Workshop on Signal Processing in Communications. The poster describes implementation of the Givens rotations using the High Speed Logarithmic Arithmetic (HSLA) library. This library is used for an efficient implementation of the floating-point arithmetic operations typical for the signal processing algorithms (including the square-root operation) in FPGA.FPL2003 Conference
Our group will present two posters at the FPL conference in Lisboa, Portugal (Sept. 1-3, 2003). The first poster describes an FPGA implementation of an adaptive lattice filter, the second poster shows a Matlab/Simulink flow for rapid FPGA prototyping.ACM UK SIGDA workshop on EDA
Our group will present two posters at the ACM UK SIGDA workshop in Southampton, UK (Sept. 11-12). The first poster analyzes dynamic reconfiguration in Atmel AT94K FPGAs. The second poster describes extensions to the Matlab/Simulink tool for FPGA prototyping.Meeting with the DG INFSO representative
ÚTIA is organising a meeting with Stephan Pascall, the representative of DG INFSO. The meeting will be held on 20 June in ÚTIA in presence of: Milos Chvojka, Ministry of Education, Youth and Sports, Vladimir Albrecht, NCP in the Czech Republic, Milan Mares, director of the ÚTIA, Karel Charvat, vise president of Czech Centrum for Strategic Studies, Jiri Kadlec, the head of dept. of Signal Processing in ÚTIA, Vladimir Marik, dept. of Cybernetics, Faculty of Electrical Engineering Czech Technical University, Karel Aim, responsible for national research program for 2004-5, scientific board chairman of the Institute of Chemical Process Fundamentals Academy of Sciences.ECS conference
Our group will present one paper at the ECS conference in Bratislava, SK (Sept. 11-12, 2003). The paper compares two recursive algorithms for blind equalization based on Constant Modulus algorithm (CMA). The work has been carried out in cooperation with Institute Nation de Telecommunication, Evry - France.UTIA takes part in the European IST Prize
Department of Signal Processing is trying to succeed with Logarithmic pipelined ALU Macros for FPGA in the most distinguished Prize for innovative products and services in the field of Information Society Technologies. The results of the European IST Prize will be announced at the IST Event in Milan on 2-4 October 2003.Articles about the project IDEAL-IST
Two articles about the project IDEAL-IST have been publicished on CORDIS web pages. See: "Transnational brokerage" or A "win-win" proposal for ACCsInternational Event on Information Society Technology, 2 June 2003, Athens
IDEALIST network is organizing an International Event on Information Society Technologies - 2nd Call for Proposals, Networking, Partner Searches and Proposals preparation on Monday, 2 June 2003 in Athens, Greece.Our group will support the specific sessions in order to help the participants formulate concrete consortia for proposal submission within the framework of IST.
For more information, see:
https://www.ekt.gr/en/news/events/ekt/2003-06-02/index.html
or contact Milada Kadlecova
Meeting at FIT
Our group is getting in contact with the Computer Architecture Group at the Faculty of Information Technology (FIT), Brno Institute of Technology. To initiate a closer cooperation we will present the interests and projects undertaken by our group members. The presentation will take place in Brno on May 15, 2003. If you are interested and would like to meet us in Brno, contact us.RAW Conference
Our group will present a poster at the Reconfigurable Architectures Workshop (RAW 2003) at Nice, France, April 22. The title of the poster is "Logarithmic Arithmetic for Real Data Types and Support for MATLAB/Simulink-based Rapid FPGA Prototyping". The aim of the poster is to outline possible rapid-prototyping design flow from Simulink to FPGA using the Real-Time Workshop and Handel-C. The idea is presented on an example where logarithmic arithemtic functions are integrated into design.ECMS Conference
Our group will present two papers at the ECMS conference in Liberec, CR (June 2-4, 2003). The first paper will describe evolutionary approaches used in FPGA design. The second paper will describe a design that uses dynamic reconfiguration of FPGA devices.NetCeE Workshops
NetCeE consortium is organizing informational workshops about many aspects of the IST Programme of the 6 Framework Programme EU. The two days workshops with topic "An introduction FP6" and "Co-ordinating EC Research projects" are going to be held 20-21 February in Krakow (Poland), 5-6 March in Riga (Latvia), and 7-8 April in PragueFor more information contact Dana Feikova or look at our NetCeE www pages
The workshop is already filled.