This design is targeted for xczu4ev board (part number: PROD-1)

Zynq UltraScale+ Design Summary

Device	xczu4ev
SpeedGrade	-1
Part	PROD-1
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	schmitt	slow	pullup	out	12
MIO 1	Quad SPI Flash	miso_mo1	schmitt	slow	pullup	inout	12
MIO 2	Quad SPI Flash	mo2	schmitt	slow	pullup	inout	12
MIO 3	Quad SPI Flash	mo3	schmitt	slow	pullup	inout	12
MIO 4	Quad SPI Flash	mosi_mi0	schmitt	slow	pullup	inout	12
MIO 5	Quad SPI Flash	n_ss_out	schmitt	slow	pullup	out	12
MIO 6	Feedback Clk	clk_for_lpbk	schmitt	slow	pullup	out	12
MIO 7	Quad SPI Flash	n_ss_out_upper	schmitt	slow	pullup	out	12
MIO 8	Quad SPI Flash	mo_upper[0]	schmitt	slow	pullup	inout	12
MIO 9	Quad SPI Flash	mo_upper[1]	schmitt	slow	pullup	inout	12
MIO 10	Quad SPI Flash	mo_upper[2]	schmitt	slow	pullup	inout	12
MIO 11	Quad SPI Flash	mo_upper[3]	schmitt	slow	pullup	inout	12
MIO 12	Quad SPI Flash	sclk_out_upper	schmitt	slow	pullup	out	12
MIO 13	SD 0	sdio0_data_out[0]	schmitt	slow	pullup	inout	12
MIO 14	SD 0	sdio0_data_out[1]	schmitt	slow	pullup	inout	12
MIO 15	SD 0	sdio0_data_out[2]	schmitt	slow	pullup	inout	12
MIO 16	SD 0	sdio0_data_out[3]	schmitt	slow	pullup	inout	12
MIO 17	SD 0	sdio0_data_out[4]	schmitt	slow	pullup	inout	12
MIO 18	SD 0	sdio0_data_out[5]	schmitt	slow	pullup	inout	12
MIO 19	SD 0	sdio0_data_out[6]	schmitt	slow	pullup	inout	12
MIO 20	SD 0	sdio0_data_out[7]	schmitt	slow	pullup	inout	12
MIO 21	SD 0	sdio0_cmd_out	schmitt	slow	pullup	inout	12
MIO 22	SD 0	sdio0_clk_out	schmitt	slow	pullup	out	12
MIO 23	SD 0	sdio0_bus_pow	schmitt	slow	pullup	out	12
MIO 24	GPIO0 MIO	gpio0[24]	schmitt	slow	pullup	inout	12
MIO 25	GPIO0 MIO	gpio0[25]	schmitt	slow	pullup	inout	12
MIO 26			schmitt	slow	pullup		12
MIO 27			schmitt	slow	pullup		12
MIO 28			schmitt	slow	pullup		12
MIO 29			schmitt	slow	pullup		12
MIO 30	UART 0	rxd	schmitt	slow	pullup	in	12
MIO 31	UART 0	txd	schmitt	slow	pullup	out	12
MIO 32			schmitt	slow	pullup		12
MIO 33			schmitt	slow	pullup		12
MIO 34			schmitt	slow	pullup		12
MIO 35			schmitt	slow	pullup		12
MIO 36			schmitt	slow	pullup		12
MIO 37			schmitt	slow	pullup		12
MIO 38	I2C 0	scl_out	schmitt	slow	pullup	inout	12
MIO 39	I2C 0	sda_out	schmitt	slow	pullup	inout	12
MIO 40			schmitt	slow	pullup		12
MIO 41			schmitt	slow	pullup		12
MIO 42			schmitt	slow	pullup		12
MIO 43			schmitt	slow	pullup		12
MIO 44			schmitt	slow	pullup		12
MIO 45			schmitt	slow	pullup		12
MIO 46	SD 1	sdio1_data_out[0]	cmos	slow	disable	inout	12
MIO 47	SD 1	sdio1_data_out[1]	cmos	slow	disable	inout	12
MIO 48	SD 1	sdio1_data_out[2]	cmos	slow	disable	inout	12
MIO 49	SD 1	sdio1_data_out[3]	cmos	slow	disable	inout	12
MIO 50	SD 1	sdio1_cmd_out	cmos	slow	disable	inout	12
MIO 51	SD 1	sdio1_clk_out	schmitt	slow	disable	out	12
MIO 52	USB 0	ulpi_clk_in	schmitt	slow	pullup	in	12
MIO 53	USB 0	ulpi_dir	schmitt	slow	pullup	in	12
MIO 54	USB 0	ulpi_tx_data[2]	schmitt	slow	pullup	inout	12
MIO 55	USB 0	ulpi_nxt	schmitt	slow	pullup	in	12
MIO 56	USB 0	ulpi_tx_data[0]	schmitt	slow	pullup	inout	12
MIO 57	USB 0	ulpi_tx_data[1]	schmitt	slow	pullup	inout	12
MIO 58	USB 0	ulpi_stp	schmitt	slow	pullup	out	12
MIO 59	USB 0	ulpi_tx_data[3]	schmitt	slow	pullup	inout	12
MIO 60	USB 0	ulpi_tx_data[4]	schmitt	slow	pullup	inout	12
MIO 61	USB 0	ulpi_tx_data[5]	schmitt	slow	pullup	inout	12
MIO 62	USB 0	ulpi_tx_data[6]	schmitt	slow	pullup	inout	12
MIO 63	USB 0	ulpi_tx_data[7]	schmitt	slow	pullup	inout	12
MIO 64	Gem 3	rgmii_tx_clk	schmitt	slow	pullup	out	12
MIO 65	Gem 3	rgmii_txd[0]	schmitt	slow	pullup	out	12
MIO 66	Gem 3	rgmii_txd[1]	schmitt	slow	pullup	out	12
MIO 67	Gem 3	rgmii_txd[2]	schmitt	slow	pullup	out	12
MIO 68	Gem 3	rgmii_txd[3]	schmitt	slow	pullup	out	12
MIO 69	Gem 3	rgmii_tx_ctl	schmitt	slow	pullup	out	12
MIO 70	Gem 3	rgmii_rx_clk	schmitt	slow	pullup	in	12
MIO 71	Gem 3	rgmii_rxd[0]	schmitt	slow	pullup	in	12
MIO 72	Gem 3	rgmii_rxd[1]	schmitt	slow	pullup	in	12
MIO 73	Gem 3	rgmii_rxd[2]	schmitt	slow	pullup	in	12
MIO 74	Gem 3	rgmii_rxd[3]	schmitt	slow	pullup	in	12
MIO 75	Gem 3	rgmii_rx_ctl	schmitt	slow	pullup	in	12
MIO 76	MDIO 3	gem3_mdc	schmitt	slow	pullup	out	12
MIO 77	MDIO 3	gem3_mdio_out	schmitt	slow	pullup	inout	12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2400.000
DPLL	PSS_REF_CLK	2400.000
VPLL	PSS_REF_CLK	2100.000
RPLL	PSS_REF_CLK	2400.000
IOPLL	PSS_REF_CLK	3000.000

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
GEM3 freq (MHz)	125	IOPLL	124.999988
USB0 freq (MHz)	250	IOPLL	249.999975
QSPI freq (MHz)	300	IOPLL	299.999970
SDIO0 freq (MHz)	200	RPLL	199.999980
SDIO1 freq (MHz)	200	RPLL	199.999980
UART0 freq (MHz)	100	IOPLL	99.999990
I2C0 freq (MHz)	100	IOPLL	99.999990
CPU_R5 freq (MHz)	500	IOPLL	499.999950
IOU_SWITCH freq (MHz)	267	RPLL	239.999976
LPD_SWITCH freq (MHz)	500	IOPLL	499.999950
LPD_LSBUS freq (MHz)	100	IOPLL	99.999990
GEM_TSU freq (MHz)	250	IOPLL	249.999975
TIMESTAMP freq (MHz)	100	PSS_REF_CLK	33.333330
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	20	IOPLL	19.999998
PCAP freq (MHz)	200	IOPLL	187.499981
DBG_LPD freq (MHz)	250	IOPLL	249.999975
ADMA freq (MHz)	500	IOPLL	499.999950
PL0 freq (MHz)	100	RPLL	99.999990
PL1 freq (MHz)	25	RPLL	24.999997
PL2 freq (MHz)	150	RPLL	149.999985
PL3 freq (MHz)	200	RPLL	199.999980
AMS freq (MHz)	50	IOPLL	49.999995
ACPU freq (MHz)	1200	APLL	1199.999880
DBG FPD freq (MHz)	250	IOPLL	249.999975
DDR_CTRL freq MHz)	600.000	DPLL	599.999940
GPU freq (MHz)	600	DPLL	599.999940
GDMA freq (MHz)	600	DPLL	599.999940
DPDMA freq (MHz)	600	DPLL	599.999940
TOPSW_MAIN freq (MHz)	533.333	VPLL	524.999947
TOPSW_LSBUS freq (MHz)	100	IOPLL	99.999990
DBG TSTMP freq (MHz)	250	IOPLL	249.999975

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1200	--
MEMORY TYPE	DDR 4	Type of memory interface
DM DBI	UDIMM
BUS WIDTH	32 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	DDR4_2400P	Speed Bin
CL	17	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	12	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	17	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	17	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	46.16	Row cycle time (ns)
T RAS MIN	32.0	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	30.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	16 Bits	Width of individual DRAM components
DEVICE CAPACITY	8192 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	1	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	2	Number of bank address pins
ROW ADDR COUNT	16	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0x7FFFFFFF	--

GT lanes information

Protocol	GT lane#	Ref Clk Sel	Ref freq (MHz)
USB0	GT Lane0	Ref Clk3	100