TABLE OF CONTENTS

Overview
Block Diagram
External Ports
Processors
   microblaze_0
   processing_system7_0
Debuggers
   debug_module
Interrupt Controllers
   microblaze_0_intc
Busses
   axi4lite_mb_0
   axi_interconnect_mb
Peripherals
   LEDs_4Bits
   bce_fp11_1x8_0_axiw_0
   bce_fp11_1x8_0_axiw_1
   bce_fp11_1x8_0_axiw_2
   bce_fp11_1x8_0_axiw_3
   irq_gen_0
IP
   chipscope_icon_0
   chipscope_ila_0
   chipscope_vio_0
   clock_generator_0
   proc_sys_reset_0
   util_bus_split_0
Timing Information
Overview TOC
Resources Used
1   Processing System
1   MicroBlaze
2   AXI Interconnect
1   AXI General Purpose IO
1   Processor System Reset Module
1   AXI Interrupt Controller
1   MicroBlaze Debug Module (MDM)
1   Clock Generator
1   IRQ_GEN
1   Utility Bus Split
1   Chipscope Integrated Controller
1   Chipscope Virtual IO (VIO)
1   Chipscope Integrated Logic Analyzer (ILA)
Specifics
Generated Fri Oct 03 09:07:28 2014
EDK Version 14.5
Device Family zynq
Device xc7z020clg484-1

Block Diagram TOC

BlockDiagram
External Ports TOC

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
SHARED RESET I 1 RESET  RESET 
LEDs_4Bits LEDs_4Bits_TRI_IO O 0:3 LEDs_4Bits_TRI_IO
clock_generator_0 CLK_N I 1 CLK  CLK 
processing_system7_0 processing_system7_0_PS_CLK I 1 processing_system7_0_PS_CLK  CLK 
processing_system7_0 processing_system7_0_PS_PORB I 1 processing_system7_0_PS_PORB
processing_system7_0 processing_system7_0_PS_SRSTB I 1 processing_system7_0_PS_SRSTB
processing_system7_0 processing_system7_0_DDR_Addr IO 0:14 processing_system7_0_DDR_Addr
processing_system7_0 processing_system7_0_DDR_BankAddr IO 0:2 processing_system7_0_DDR_BankAddr
processing_system7_0 processing_system7_0_DDR_CAS_n IO 1 processing_system7_0_DDR_CAS_n
processing_system7_0 processing_system7_0_DDR_CKE IO 1 processing_system7_0_DDR_CKE
processing_system7_0 processing_system7_0_DDR_CS_n IO 1 processing_system7_0_DDR_CS_n
processing_system7_0 processing_system7_0_DDR_Clk IO 1 processing_system7_0_DDR_Clk  CLK 
processing_system7_0 processing_system7_0_DDR_Clk_n IO 1 processing_system7_0_DDR_Clk_n  CLK 
processing_system7_0 processing_system7_0_DDR_DM IO 0:3 processing_system7_0_DDR_DM
processing_system7_0 processing_system7_0_DDR_DQ IO 0:31 processing_system7_0_DDR_DQ
processing_system7_0 processing_system7_0_DDR_DQS IO 0:3 processing_system7_0_DDR_DQS
processing_system7_0 processing_system7_0_DDR_DQS_n IO 0:3 processing_system7_0_DDR_DQS_n
processing_system7_0 processing_system7_0_DDR_DRSTB IO 1 processing_system7_0_DDR_DRSTB  RESET 
processing_system7_0 processing_system7_0_DDR_ODT IO 1 processing_system7_0_DDR_ODT
processing_system7_0 processing_system7_0_DDR_RAS_n IO 1 processing_system7_0_DDR_RAS_n
processing_system7_0 processing_system7_0_DDR_VRN IO 1 processing_system7_0_DDR_VRN
processing_system7_0 processing_system7_0_DDR_VRP IO 1 processing_system7_0_DDR_VRP
processing_system7_0 processing_system7_0_MIO IO 0:53 processing_system7_0_MIO
processing_system7_0 processing_system7_0_DDR_WEB_pin O 1 processing_system7_0_DDR_WEB
clock_generator_0 CLK_P I 1 CLK  CLK 


Processors TOC

microblaze_0   MicroBlaze
The MicroBlaze 32 bit soft processor

IP Specs
Core Version Documentation
microblaze 8.50.a IP


microblaze_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MB_RESET I 1 proc_sys_reset_0_MB_Reset
1 CLK I 1 clk_100_0000MHz
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
M_AXI_DP MASTER AXI axi4lite_mb_0 9 Peripherals.
M_AXI_IC MASTER AXI axi_interconnect_mb processing_system7_0
M_AXI_DC MASTER AXI axi_interconnect_mb processing_system7_0
DEBUG TARGET XIL_MBDEBUG3 microblaze_0_debug debug_module
INTERRUPT TARGET XIL_MBINTERRUPT microblaze_0_interrupt microblaze_0_intc


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SCO 0
C_FREQ 0
C_DATA_SIZE 32
C_DYNAMIC_BUS_SIZING 1
C_FAMILY virtex5
C_INSTANCE microblaze
C_AVOID_PRIMITIVES 0
C_FAULT_TOLERANT 0
C_ECC_USE_CE_EXCEPTION 0
C_LOCKSTEP_SLAVE 0
C_ENDIANNESS 0
C_AREA_OPTIMIZED 0
C_OPTIMIZATION 0
C_INTERCONNECT 2
C_STREAM_INTERCONNECT 0
C_BASE_VECTORS 0x30000000
C_DPLB_DWIDTH 32
C_DPLB_NATIVE_DWIDTH 32
C_DPLB_BURST_EN 0
C_DPLB_P2P 0
C_IPLB_DWIDTH 32
C_IPLB_NATIVE_DWIDTH 32
C_IPLB_BURST_EN 0
C_IPLB_P2P 0
C_M_AXI_DP_SUPPORTS_THREADS 0
C_M_AXI_DP_THREAD_ID_WIDTH 1
C_M_AXI_DP_SUPPORTS_READ 1
C_M_AXI_DP_SUPPORTS_WRITE 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST 0
C_M_AXI_DP_DATA_WIDTH 32
C_M_AXI_DP_ADDR_WIDTH 32
C_M_AXI_DP_PROTOCOL AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING 1
C_M_AXI_IP_SUPPORTS_THREADS 0
C_M_AXI_IP_THREAD_ID_WIDTH 1
C_M_AXI_IP_SUPPORTS_READ 1
C_M_AXI_IP_SUPPORTS_WRITE 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST 0
C_M_AXI_IP_DATA_WIDTH 32
C_M_AXI_IP_ADDR_WIDTH 32
C_M_AXI_IP_PROTOCOL AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING 1
C_D_AXI 0
C_D_PLB 0
C_D_LMB 1
C_I_AXI 0
C_I_PLB 0
C_I_LMB 1
C_USE_MSR_INSTR 1
C_USE_PCMP_INSTR 1
C_USE_BARREL 1
C_USE_DIV 0
C_USE_HW_MUL 1
C_USE_FPU 1
C_USE_REORDER_INSTR 1
C_UNALIGNED_EXCEPTIONS 0
C_ILL_OPCODE_EXCEPTION 0
C_M_AXI_I_BUS_EXCEPTION 0
C_M_AXI_D_BUS_EXCEPTION 0
C_IPLB_BUS_EXCEPTION 0
C_DPLB_BUS_EXCEPTION 0
C_DIV_ZERO_EXCEPTION 0
C_FPU_EXCEPTION 0
C_FSL_EXCEPTION 0
C_USE_STACK_PROTECTION 0
C_PVR 0
C_PVR_USER1 0x00
C_PVR_USER2 0x00000000
C_DEBUG_ENABLED 1
C_NUMBER_OF_PC_BRK 1
C_NUMBER_OF_RD_ADDR_BRK 0
C_NUMBER_OF_WR_ADDR_BRK 0
C_INTERRUPT_IS_EDGE 0
C_EDGE_IS_POSITIVE 1
C_RESET_MSR 0x00000000
C_OPCODE_0x0_ILLEGAL 0
C_FSL_LINKS 0
C_FSL_DATA_SIZE 32
C_USE_EXTENDED_FSL_INSTR 0
C_M0_AXIS_PROTOCOL GENERIC
C_S0_AXIS_PROTOCOL GENERIC
C_M1_AXIS_PROTOCOL GENERIC
C_S1_AXIS_PROTOCOL GENERIC
C_M2_AXIS_PROTOCOL GENERIC
C_S2_AXIS_PROTOCOL GENERIC
C_M3_AXIS_PROTOCOL GENERIC
C_S3_AXIS_PROTOCOL GENERIC
C_M4_AXIS_PROTOCOL GENERIC
C_S4_AXIS_PROTOCOL GENERIC
C_M5_AXIS_PROTOCOL GENERIC
C_S5_AXIS_PROTOCOL GENERIC
C_M6_AXIS_PROTOCOL GENERIC
C_S6_AXIS_PROTOCOL GENERIC
C_M7_AXIS_PROTOCOL GENERIC
C_S7_AXIS_PROTOCOL GENERIC
C_M8_AXIS_PROTOCOL GENERIC
C_S8_AXIS_PROTOCOL GENERIC
C_M9_AXIS_PROTOCOL GENERIC
C_S9_AXIS_PROTOCOL GENERIC
C_M10_AXIS_PROTOCOL GENERIC
C_S10_AXIS_PROTOCOL GENERIC
C_M11_AXIS_PROTOCOL GENERIC
C_S11_AXIS_PROTOCOL GENERIC
C_M12_AXIS_PROTOCOL GENERIC
C_S12_AXIS_PROTOCOL GENERIC
C_M13_AXIS_PROTOCOL GENERIC
C_S13_AXIS_PROTOCOL GENERIC
C_M14_AXIS_PROTOCOL GENERIC
 
Name Value
C_S14_AXIS_PROTOCOL GENERIC
C_M15_AXIS_PROTOCOL GENERIC
C_S15_AXIS_PROTOCOL GENERIC
C_M0_AXIS_DATA_WIDTH 32
C_S0_AXIS_DATA_WIDTH 32
C_M1_AXIS_DATA_WIDTH 32
C_S1_AXIS_DATA_WIDTH 32
C_M2_AXIS_DATA_WIDTH 32
C_S2_AXIS_DATA_WIDTH 32
C_M3_AXIS_DATA_WIDTH 32
C_S3_AXIS_DATA_WIDTH 32
C_M4_AXIS_DATA_WIDTH 32
C_S4_AXIS_DATA_WIDTH 32
C_M5_AXIS_DATA_WIDTH 32
C_S5_AXIS_DATA_WIDTH 32
C_M6_AXIS_DATA_WIDTH 32
C_S6_AXIS_DATA_WIDTH 32
C_M7_AXIS_DATA_WIDTH 32
C_S7_AXIS_DATA_WIDTH 32
C_M8_AXIS_DATA_WIDTH 32
C_S8_AXIS_DATA_WIDTH 32
C_M9_AXIS_DATA_WIDTH 32
C_S9_AXIS_DATA_WIDTH 32
C_M10_AXIS_DATA_WIDTH 32
C_S10_AXIS_DATA_WIDTH 32
C_M11_AXIS_DATA_WIDTH 32
C_S11_AXIS_DATA_WIDTH 32
C_M12_AXIS_DATA_WIDTH 32
C_S12_AXIS_DATA_WIDTH 32
C_M13_AXIS_DATA_WIDTH 32
C_S13_AXIS_DATA_WIDTH 32
C_M14_AXIS_DATA_WIDTH 32
C_S14_AXIS_DATA_WIDTH 32
C_M15_AXIS_DATA_WIDTH 32
C_S15_AXIS_DATA_WIDTH 32
C_ICACHE_BASEADDR 0x30000000
C_ICACHE_HIGHADDR 0x3FFFFFFF
C_USE_ICACHE 1
C_ALLOW_ICACHE_WR 1
C_ADDR_TAG_BITS 17
C_CACHE_BYTE_SIZE 8192
C_ICACHE_USE_FSL 1
C_ICACHE_LINE_LEN 8
C_ICACHE_ALWAYS_USED 1
C_ICACHE_INTERFACE 0
C_ICACHE_VICTIMS 0
C_ICACHE_STREAMS 0
C_ICACHE_FORCE_TAG_LUTRAM 0
C_ICACHE_DATA_WIDTH 0
C_M_AXI_IC_SUPPORTS_THREADS 0
C_M_AXI_IC_THREAD_ID_WIDTH 1
C_M_AXI_IC_SUPPORTS_READ 1
C_M_AXI_IC_SUPPORTS_WRITE 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST 0
C_M_AXI_IC_DATA_WIDTH 32
C_M_AXI_IC_ADDR_WIDTH 32
C_M_AXI_IC_PROTOCOL AXI4
C_M_AXI_IC_USER_VALUE 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS 1
C_M_AXI_IC_AWUSER_WIDTH 5
C_M_AXI_IC_ARUSER_WIDTH 5
C_M_AXI_IC_WUSER_WIDTH 1
C_M_AXI_IC_RUSER_WIDTH 1
C_M_AXI_IC_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING 2
C_DCACHE_BASEADDR 0x30000000
C_DCACHE_HIGHADDR 0x3FFFFFFF
C_USE_DCACHE 1
C_ALLOW_DCACHE_WR 1
C_DCACHE_ADDR_TAG 17
C_DCACHE_BYTE_SIZE 8192
C_DCACHE_USE_FSL 1
C_DCACHE_LINE_LEN 8
C_DCACHE_ALWAYS_USED 1
C_DCACHE_INTERFACE 0
C_DCACHE_USE_WRITEBACK 0
C_DCACHE_VICTIMS 0
C_DCACHE_FORCE_TAG_LUTRAM 0
C_DCACHE_DATA_WIDTH 0
C_M_AXI_DC_SUPPORTS_THREADS 0
C_M_AXI_DC_THREAD_ID_WIDTH 1
C_M_AXI_DC_SUPPORTS_READ 1
C_M_AXI_DC_SUPPORTS_WRITE 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST 0
C_M_AXI_DC_DATA_WIDTH 32
C_M_AXI_DC_ADDR_WIDTH 32
C_M_AXI_DC_PROTOCOL AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS 0
C_M_AXI_DC_USER_VALUE 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS 1
C_M_AXI_DC_AWUSER_WIDTH 5
C_M_AXI_DC_ARUSER_WIDTH 5
C_M_AXI_DC_WUSER_WIDTH 1
C_M_AXI_DC_RUSER_WIDTH 1
C_M_AXI_DC_BUSER_WIDTH 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING 32
C_USE_MMU 0
C_MMU_DTLB_SIZE 4
C_MMU_ITLB_SIZE 2
C_MMU_TLB_ACCESS 3
C_MMU_ZONES 16
C_MMU_PRIVILEGED_INSTR 0
C_USE_INTERRUPT 0
C_USE_EXT_BRK 0
C_USE_EXT_NM_BRK 0
C_USE_BRANCH_TARGET_CACHE 0
C_BRANCH_TARGET_CACHE_SIZE 0
C_PC_WIDTH 32
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


processing_system7_0   Processing System
Processing System wrapper for Series 7

IP Specs
Core Version Documentation
processing_system7 4.03.a IP


processing_system7_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MIO IO 1 processing_system7_0_MIO
1 PS_SRSTB I 1 processing_system7_0_PS_SRSTB
2 PS_CLK I 1 processing_system7_0_PS_CLK
3 PS_PORB I 1 processing_system7_0_PS_PORB
4 DDR_Clk IO 1 processing_system7_0_DDR_Clk
5 DDR_Clk_n IO 1 processing_system7_0_DDR_Clk_n
6 DDR_CKE IO 1 processing_system7_0_DDR_CKE
7 DDR_CS_n IO 1 processing_system7_0_DDR_CS_n
8 DDR_RAS_n IO 1 processing_system7_0_DDR_RAS_n
9 DDR_CAS_n IO 1 processing_system7_0_DDR_CAS_n
10 DDR_WEB O 1 processing_system7_0_DDR_WEB
11 DDR_BankAddr IO 1 processing_system7_0_DDR_BankAddr
12 DDR_Addr IO 1 processing_system7_0_DDR_Addr
13 DDR_ODT IO 1 processing_system7_0_DDR_ODT
14 DDR_DRSTB IO 1 processing_system7_0_DDR_DRSTB
15 DDR_DQ IO 1 processing_system7_0_DDR_DQ
16 DDR_DM IO 1 processing_system7_0_DDR_DM
17 DDR_DQS IO 1 processing_system7_0_DDR_DQS
18 DDR_DQS_n IO 1 processing_system7_0_DDR_DQS_n
19 DDR_VRN IO 1 processing_system7_0_DDR_VRN
20 DDR_VRP IO 1 processing_system7_0_DDR_VRP
21 S_AXI_GP0_ACLK I 1 clk_100_0000MHz
22 S_AXI_HP0_ACLK I 1 clk_100_0000MHz
23 FCLK_RESET0_N O 1 processing_system7_0_FCLK_RESET0_N
24 S_AXI_HP1_ACLK I 1 clk_100_0000MHz
25 GPIO_O O 1 psGpio_o
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI_GP0 SLAVE AXI axi4lite_mb_0 9 Peripherals.
S_AXI_HP1 SLAVE AXI axi_interconnect_mb microblaze_0
S_AXI_HP0 SLAVE AXI axi_interconnect_mb microblaze_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EN_EMIO_CAN0 0
C_EN_EMIO_CAN1 0
C_EN_EMIO_ENET0 0
C_EN_EMIO_ENET1 0
C_EN_EMIO_GPIO 1
C_EN_EMIO_I2C0 0
C_EN_EMIO_I2C1 0
C_EN_EMIO_PJTAG 0
C_EN_EMIO_SDIO0 0
C_EN_EMIO_CD_SDIO0 0
C_EN_EMIO_WP_SDIO0 0
C_EN_EMIO_SDIO1 0
C_EN_EMIO_CD_SDIO1 0
C_EN_EMIO_WP_SDIO1 0
C_EN_EMIO_SPI0 0
C_EN_EMIO_SPI1 0
C_EN_EMIO_UART0 0
C_EN_EMIO_UART1 0
C_EN_EMIO_MODEM_UART0 0
C_EN_EMIO_MODEM_UART1 0
C_EN_EMIO_TTC0 1
C_EN_EMIO_TTC1 0
C_EN_EMIO_WDT 1
C_EN_EMIO_TRACE 0
C_USE_M_AXI_GP0 0
C_USE_M_AXI_GP1 0
C_USE_S_AXI_GP0 1
C_USE_S_AXI_GP1 0
C_USE_S_AXI_ACP 0
C_USE_S_AXI_HP0 1
C_USE_S_AXI_HP1 1
C_USE_S_AXI_HP2 0
C_USE_S_AXI_HP3 0
C_S_AXI_GP0_ENABLE_LOWOCM_DDR 0
C_S_AXI_GP1_ENABLE_LOWOCM_DDR 0
C_S_AXI_ACP_ENABLE_HIGHOCM 0
C_S_AXI_HP0_ENABLE_HIGHOCM 0
C_S_AXI_HP1_ENABLE_HIGHOCM 0
C_S_AXI_HP2_ENABLE_HIGHOCM 0
C_S_AXI_HP3_ENABLE_HIGHOCM 0
C_USE_DMA0 0
C_USE_DMA1 0
C_USE_DMA2 0
C_USE_DMA3 0
C_USE_TRACE 0
C_INCLUDE_TRACE_BUFFER 0
C_TRACE_BUFFER_FIFO_SIZE 128
USE_TRACE_DATA_EDGE_DETECTOR 0
C_TRACE_BUFFER_CLOCK_DELAY 12
C_USE_CROSS_TRIGGER 0
C_USE_CR_FABRIC 1
C_USE_AXI_FABRIC_IDLE 0
C_USE_DDR_BYPASS 0
C_USE_FABRIC_INTERRUPT 1
C_USE_PROC_EVENT_BUS 0
C_EN_EMIO_SRAM_INT 0
C_EMIO_GPIO_WIDTH 64
C_INCLUDE_ACP_TRANS_CHECK 0
C_USE_DEFAULT_ACP_USER_VAL 0
C_S_AXI_ACP_ARUSER_VAL 31
C_S_AXI_ACP_AWUSER_VAL 31
C_DQ_WIDTH 32
C_DQS_WIDTH 4
C_DM_WIDTH 4
C_MIO_PRIMITIVE 54
C_PACKAGE_NAME clg484
C_PS7_SI_REV PRODUCTION
C_UART_BAUD_RATE 115200
C_DDR_RAM_BASEADDR 0x00000000
C_DDR_RAM_HIGHADDR 0x3FFFFFFF
C_UART0_BASEADDR 0xE0000000
C_UART0_HIGHADDR 0xE0000FFF
C_UART1_BASEADDR 0xE0001000
C_UART1_HIGHADDR 0xE0001FFF
C_I2C0_BASEADDR 0xE0004000
C_I2C0_HIGHADDR 0xE0004FFF
C_I2C1_BASEADDR 0xE0005000
C_I2C1_HIGHADDR 0xE0005FFF
C_SPI0_BASEADDR 0xE0006000
C_SPI0_HIGHADDR 0xE0006FFF
C_SPI1_BASEADDR 0xE0007000
C_SPI1_HIGHADDR 0xE0007FFF
C_CAN0_BASEADDR 0xE0008000
C_CAN0_HIGHADDR 0xE0008FFF
C_CAN1_BASEADDR 0xE0009000
C_CAN1_HIGHADDR 0xE0009FFF
C_GPIO_BASEADDR 0xE000A000
C_GPIO_HIGHADDR 0xE000AFFF
C_ENET0_BASEADDR 0xE000B000
C_ENET0_HIGHADDR 0xE000BFFF
C_ENET1_BASEADDR 0xE000C000
C_ENET1_HIGHADDR 0xE000CFFF
C_SDIO0_BASEADDR 0xE0100000
C_SDIO0_HIGHADDR 0xE0100FFF
C_SDIO1_BASEADDR 0xE0101000
C_SDIO1_HIGHADDR 0xE0101FFF
C_USB0_BASEADDR 0xE0002000
C_USB0_HIGHADDR 0xE0002FFF
C_USB1_BASEADDR 0xE0003000
C_USB1_HIGHADDR 0xE0003FFF
C_TTC0_BASEADDR 0xF8001000
C_TTC0_HIGHADDR 0xF8001FFF
C_TTC1_BASEADDR 0xF8002000
C_TTC1_HIGHADDR 0xF8002FFF
C_M_AXI_GP0_PROTOCOL AXI3
C_M_AXI_GP0_ID_WIDTH 12
C_M_AXI_GP0_ADDR_WIDTH 32
C_M_AXI_GP0_DATA_WIDTH 32
C_M_AXI_GP0_ENABLE_STATIC_REMAP 0
C_M_AXI_GP0_SUPPORTS_NARROW_BURST 0
C_M_AXI_GP0_SUPPORTS_REORDERING 0
C_INTERCONNECT_M_AXI_GP0_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_GP0_READ_ISSUING 8
C_M_AXI_GP1_PROTOCOL AXI3
C_M_AXI_GP1_ID_WIDTH 12
C_M_AXI_GP1_ADDR_WIDTH 32
C_M_AXI_GP1_DATA_WIDTH 32
C_M_AXI_GP1_ENABLE_STATIC_REMAP 0
 
Name Value
C_M_AXI_GP1_SUPPORTS_NARROW_BURST 0
C_M_AXI_GP1_SUPPORTS_REORDERING 0
C_INTERCONNECT_M_AXI_GP1_WRITE_ISSUING 8
C_INTERCONNECT_M_AXI_GP1_READ_ISSUING 8
C_S_AXI_GP0_PROTOCOL AXI3
C_S_AXI_GP0_ID_WIDTH 6
C_S_AXI_GP0_ADDR_WIDTH 32
C_S_AXI_GP0_DATA_WIDTH 32
C_INTERCONNECT_S_AXI_GP0_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_GP0_READ_ACCEPTANCE 8
C_S_AXI_GP1_PROTOCOL AXI3
C_S_AXI_GP1_ID_WIDTH 6
C_S_AXI_GP1_ADDR_WIDTH 32
C_S_AXI_GP1_DATA_WIDTH 32
C_INTERCONNECT_S_AXI_GP1_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_GP1_READ_ACCEPTANCE 8
C_S_AXI_ACP_PROTOCOL AXI3
C_S_AXI_ACP_ID_WIDTH 3
C_S_AXI_ACP_ADDR_WIDTH 32
C_S_AXI_ACP_DATA_WIDTH 64
C_S_AXI_ACP_SUPPORTS_USER_SIGNALS 1
C_S_AXI_ACP_ARUSER_WIDTH 5
C_S_AXI_ACP_AWUSER_WIDTH 5
C_INTERCONNECT_S_AXI_ACP_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_ACP_READ_ACCEPTANCE 8
C_S_AXI_HP0_PROTOCOL AXI3
C_S_AXI_HP0_ID_WIDTH 6
C_S_AXI_HP0_ADDR_WIDTH 32
C_S_AXI_HP0_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP0_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP0_READ_ACCEPTANCE 8
C_S_AXI_HP1_PROTOCOL AXI3
C_S_AXI_HP1_ID_WIDTH 6
C_S_AXI_HP1_ADDR_WIDTH 32
C_S_AXI_HP1_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP1_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP1_READ_ACCEPTANCE 8
C_S_AXI_HP2_PROTOCOL AXI3
C_S_AXI_HP2_ID_WIDTH 6
C_S_AXI_HP2_ADDR_WIDTH 32
C_S_AXI_HP2_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP2_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP2_READ_ACCEPTANCE 8
C_S_AXI_HP3_PROTOCOL AXI3
C_S_AXI_HP3_ID_WIDTH 6
C_S_AXI_HP3_ADDR_WIDTH 32
C_S_AXI_HP3_DATA_WIDTH 64
C_INTERCONNECT_S_AXI_HP3_WRITE_ACCEPTANCE 8
C_INTERCONNECT_S_AXI_HP3_READ_ACCEPTANCE 8
C_S_AXI_GP0_BASEADDR 0xE0000000
C_S_AXI_GP0_HIGHADDR 0xFFFFFFFF
C_S_AXI_GP0_LOWOCM_DDR_BASEADDR 0x00000000
C_S_AXI_GP0_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF
C_S_AXI_GP1_BASEADDR 0xE0000000
C_S_AXI_GP1_HIGHADDR 0xFFFFFFFF
C_S_AXI_GP1_LOWOCM_DDR_BASEADDR 0x00000000
C_S_AXI_GP1_LOWOCM_DDR_HIGHADDR 0x3FFFFFFF
C_S_AXI_ACP_BASEADDR 0x00000000
C_S_AXI_ACP_HIGHADDR 0x3FFFFFFF
C_S_AXI_ACP_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_ACP_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP0_BASEADDR 0x30000000
C_S_AXI_HP0_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP0_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP0_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP1_BASEADDR 0x30000000
C_S_AXI_HP1_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP1_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP1_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP2_BASEADDR 0x00000000
C_S_AXI_HP2_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP2_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP2_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_S_AXI_HP3_BASEADDR 0x00000000
C_S_AXI_HP3_HIGHADDR 0x3FFFFFFF
C_S_AXI_HP3_HIGHOCM_BASEADDR 0xFFFC0000
C_S_AXI_HP3_HIGHOCM_HIGHADDR 0xFFFFFFFF
C_M_AXI_GP0_SUPPORTS_THREADS 1
C_M_AXI_GP0_THREAD_ID_WIDTH 12
C_M_AXI_GP1_SUPPORTS_THREADS 1
C_M_AXI_GP1_THREAD_ID_WIDTH 12
C_NUM_F2P_INTR_INPUTS 2
C_EN_DDR 1
C_EN_SMC 0
C_EN_QSPI 1
C_EN_CAN0 1
C_EN_CAN1 0
C_EN_ENET0 1
C_EN_ENET1 0
C_EN_GPIO 1
C_EN_I2C0 1
C_EN_I2C1 0
C_EN_PJTAG 0
C_EN_SDIO0 1
C_EN_SDIO1 0
C_EN_SPI0 0
C_EN_SPI1 0
C_EN_UART0 0
C_EN_UART1 1
C_EN_MODEM_UART0 0
C_EN_MODEM_UART1 0
C_EN_TTC0 1
C_EN_TTC1 0
C_EN_WDT 1
C_EN_TRACE 0
C_EN_USB0 1
C_EN_USB1 0
C_EN_4K_TIMER 0
C_FCLK_CLK0_FREQ 50000000
C_FCLK_CLK1_FREQ 50000000
C_FCLK_CLK2_FREQ 50000000
C_FCLK_CLK3_FREQ 50000000
C_FCLK_CLK0_BUF TRUE
C_FCLK_CLK1_BUF TRUE
C_FCLK_CLK2_BUF TRUE
C_FCLK_CLK3_BUF TRUE
C_INTERCONNECT_S_AXI_HP0_MASTERS microblaze_0.M_AXI_IC
C_INTERCONNECT_S_AXI_HP1_MASTERS microblaze_0.M_AXI_DC
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Debuggers TOC

debug_module   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

IP Specs
Core Version Documentation
mdm 2.10.a IP


debug_module IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Debug_SYS_Rst O 1 proc_sys_reset_0_MB_Debug_Sys_Rst
1 S_AXI_ACLK I 1 clk_100_0000MHz
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MBDEBUG_0 INITIATOR XIL_MBDEBUG3 microblaze_0_debug microblaze_0
S_AXI SLAVE AXI axi4lite_mb_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_JTAG_CHAIN 2
C_INTERCONNECT 2
C_BASEADDR 0x42000000
C_HIGHADDR 0x4200FFFF
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 3
 
Name Value
C_SPLB_NUM_MASTERS 8
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_MB_DBG_PORTS 1
C_USE_UART 1
C_USE_BSCAN 0
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_PROTOCOL AXI4LITE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Interrupt Controllers TOC

microblaze_0_intc   AXI Interrupt Controller
intc core attached to the AXI

IP Specs
Core Version Documentation
axi_intc 1.03.a IP


microblaze_0_intc IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 INTR I 1 irq_gen_0_IRQ
2 Processor_clk I 1 clk_100_0000MHz
3 Processor_rst I 1 proc_sys_reset_0_MB_Reset
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
INTERRUPT INITIATOR XIL_MBINTERRUPT microblaze_0_interrupt microblaze_0
S_AXI SLAVE AXI axi4lite_mb_0 9 Peripherals.
Interrupt Priorities
Priority SIG MODULE
0 irq_gen_0_IRQ irq_gen_0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_intc_inst
C_BASEADDR 0x41000000
C_HIGHADDR 0x41000FFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_NUM_INTR_INPUTS 2
C_KIND_OF_INTR 0xFFFFFFFF
C_KIND_OF_EDGE 0xFFFFFFFF
C_KIND_OF_LVL 0xFFFFFFFF
C_HAS_IPR 1
C_HAS_SIE 1
 
Name Value
C_HAS_CIE 1
C_HAS_IVR 1
C_IRQ_IS_LEVEL 1
C_IRQ_ACTIVE 1
C_DISABLE_SYNCHRONIZERS 0
C_MB_CLK_NOT_CONNECTED 0
C_HAS_FAST 1
C_S_AXI_PROTOCOL AXI4LITE
C_IVAR_RESET_VALUE 0x00000010
C_ENABLE_ASYNC 0
C_EN_CASCADE_MODE 0
C_CASCADE_MASTER 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOC

axi4lite_mb_0   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.06.a IP


axi4lite_mb_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 interconnect_aclk I 1 clk_100_0000MHz
1 INTERCONNECT_ARESETN I 1 proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER M_AXI_DP
processing_system7_0 SLAVE S_AXI_GP0
LEDs_4Bits SLAVE S_AXI
microblaze_0_intc SLAVE S_AXI
debug_module SLAVE S_AXI
irq_gen_0 SLAVE S_AXI
bce_fp11_1x8_0_axiw_0 SLAVE S_AXI
bce_fp11_1x8_0_axiw_1 SLAVE S_AXI
bce_fp11_1x8_0_axiw_2 SLAVE S_AXI
bce_fp11_1x8_0_axiw_3 SLAVE S_AXI


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 0
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


axi_interconnect_mb   AXI Interconnect
AXI4 Memory-Mapped Interconnect

IP Specs
Core Version Documentation
axi_interconnect 1.06.a IP


axi_interconnect_mb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 INTERCONNECT_ACLK I 1 clk_100_0000MHz
1 INTERCONNECT_ARESETN I 1 proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER M_AXI_IC
microblaze_0 MASTER M_AXI_DC
processing_system7_0 SLAVE S_AXI_HP1
processing_system7_0 SLAVE S_AXI_HP0


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY rtl
C_BASEFAMILY rtl
C_NUM_SLAVE_SLOTS 1
C_NUM_MASTER_SLOTS 1
C_AXI_ID_WIDTH 1
C_AXI_ADDR_WIDTH 32
C_AXI_DATA_MAX_WIDTH 32
C_S_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH 32
C_S_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_M_AXI_HIGH_ADDR 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_BASE_ID 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT 0b0000000000000000
C_S_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_M_AXI_ACLK_RATIO 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO 1
C_S_AXI_SUPPORTS_WRITE 0b1111111111111111
C_S_AXI_SUPPORTS_READ 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE 0b1111111111111111
C_M_AXI_SUPPORTS_READ 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS 0
C_AXI_AWUSER_WIDTH 1
C_AXI_ARUSER_WIDTH 1
C_AXI_WUSER_WIDTH 1
C_AXI_RUSER_WIDTH 1
C_AXI_BUSER_WIDTH 1
C_AXI_CONNECTIVITY 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
 
Name Value
C_M_AXI_READ_ISSUING 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY 0b0000000000000000
C_S_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER 0
C_INTERCONNECT_CONNECTIVITY_MODE 1
C_USE_CTRL_PORT 0
C_USE_INTERRUPT 1
C_RANGE_CHECK 2
C_S_AXI_CTRL_PROTOCOL AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH 32
C_S_AXI_CTRL_DATA_WIDTH 32
C_BASEADDR 0xFFFFFFFF
C_HIGHADDR 0x00000000
C_DEBUG 0
C_S_AXI_DEBUG_SLOT 0
C_M_AXI_DEBUG_SLOT 0
C_MAX_DEBUG_THREADS 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOC

LEDs_4Bits   AXI General Purpose IO
General Purpose Input/Output (GPIO) core for the AXI bus.

IP Specs
Core Version Documentation
axi_gpio 1.01.b IP


LEDs_4Bits IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 GPIO_IO_O O 1 LEDs_4Bits_TRI_IO
1 S_AXI_ACLK I 1 clk_100_0000MHz
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_mb_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_INSTANCE axi_gpio_inst
C_BASEADDR 0x40000000
C_HIGHADDR 0x4000FFFF
C_S_AXI_ADDR_WIDTH 9
C_S_AXI_DATA_WIDTH 32
C_GPIO_WIDTH 4
C_GPIO2_WIDTH 32
C_ALL_INPUTS 0
 
Name Value
C_ALL_INPUTS_2 0
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xFFFFFFFF
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xFFFFFFFF
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


bce_fp11_1x8_0_axiw_0


IP Specs
Core Version
bce_fp11_1x8_0_axiw 1.10.a


bce_fp11_1x8_0_axiw_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 axi_aclk I 1 clk_100_0000MHz
1 sysgen_clk I 1 clk_100_0000MHz
2 btn4b I 1 net_gnd
3 dip4b I 1 net_gnd
4 gpi8b I 1 net_gnd
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_mb_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x78700000
C_HIGHADDR 0x787FFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ID_WIDTH 1
C_S_AXI_SUPPORT_BURST 0
C_MEMMAP_Z8 0x08000
C_MEMMAP_Z8_N_BITS 32
C_MEMMAP_Z8_BIN_PT 0
C_MEMMAP_Z8_DEPTH 1024
C_MEMMAP_B8 0x09000
C_MEMMAP_B8_N_BITS 32
C_MEMMAP_B8_BIN_PT 0
C_MEMMAP_B8_DEPTH 1024
C_MEMMAP_A8 0x0A000
C_MEMMAP_A8_N_BITS 32
C_MEMMAP_A8_BIN_PT 0
C_MEMMAP_A8_DEPTH 1024
C_MEMMAP_Z7 0x0B000
C_MEMMAP_Z7_N_BITS 32
C_MEMMAP_Z7_BIN_PT 0
C_MEMMAP_Z7_DEPTH 1024
C_MEMMAP_B7 0x0C000
C_MEMMAP_B7_N_BITS 32
C_MEMMAP_B7_BIN_PT 0
C_MEMMAP_B7_DEPTH 1024
C_MEMMAP_A7 0x0D000
C_MEMMAP_A7_N_BITS 32
C_MEMMAP_A7_BIN_PT 0
C_MEMMAP_A7_DEPTH 1024
C_MEMMAP_Z6 0x0E000
C_MEMMAP_Z6_N_BITS 32
C_MEMMAP_Z6_BIN_PT 0
C_MEMMAP_Z6_DEPTH 1024
C_MEMMAP_B6 0x0F000
C_MEMMAP_B6_N_BITS 32
C_MEMMAP_B6_BIN_PT 0
C_MEMMAP_B6_DEPTH 1024
C_MEMMAP_A6 0x10000
C_MEMMAP_A6_N_BITS 32
C_MEMMAP_A6_BIN_PT 0
C_MEMMAP_A6_DEPTH 1024
C_MEMMAP_Z5 0x11000
C_MEMMAP_Z5_N_BITS 32
C_MEMMAP_Z5_BIN_PT 0
C_MEMMAP_Z5_DEPTH 1024
C_MEMMAP_B5 0x12000
C_MEMMAP_B5_N_BITS 32
C_MEMMAP_B5_BIN_PT 0
C_MEMMAP_B5_DEPTH 1024
C_MEMMAP_A5 0x13000
C_MEMMAP_A5_N_BITS 32
C_MEMMAP_A5_BIN_PT 0
C_MEMMAP_A5_DEPTH 1024
C_MEMMAP_Z4 0x14000
C_MEMMAP_Z4_N_BITS 32
C_MEMMAP_Z4_BIN_PT 0
C_MEMMAP_Z4_DEPTH 1024
C_MEMMAP_B4 0x15000
 
Name Value
C_MEMMAP_B4_N_BITS 32
C_MEMMAP_B4_BIN_PT 0
C_MEMMAP_B4_DEPTH 1024
C_MEMMAP_A4 0x16000
C_MEMMAP_A4_N_BITS 32
C_MEMMAP_A4_BIN_PT 0
C_MEMMAP_A4_DEPTH 1024
C_MEMMAP_Z3 0x17000
C_MEMMAP_Z3_N_BITS 32
C_MEMMAP_Z3_BIN_PT 0
C_MEMMAP_Z3_DEPTH 1024
C_MEMMAP_B3 0x18000
C_MEMMAP_B3_N_BITS 32
C_MEMMAP_B3_BIN_PT 0
C_MEMMAP_B3_DEPTH 1024
C_MEMMAP_A3 0x19000
C_MEMMAP_A3_N_BITS 32
C_MEMMAP_A3_BIN_PT 0
C_MEMMAP_A3_DEPTH 1024
C_MEMMAP_Z2 0x1A000
C_MEMMAP_Z2_N_BITS 32
C_MEMMAP_Z2_BIN_PT 0
C_MEMMAP_Z2_DEPTH 1024
C_MEMMAP_B2 0x1B000
C_MEMMAP_B2_N_BITS 32
C_MEMMAP_B2_BIN_PT 0
C_MEMMAP_B2_DEPTH 1024
C_MEMMAP_A2 0x1C000
C_MEMMAP_A2_N_BITS 32
C_MEMMAP_A2_BIN_PT 0
C_MEMMAP_A2_DEPTH 1024
C_MEMMAP_Z1 0x1D000
C_MEMMAP_Z1_N_BITS 32
C_MEMMAP_Z1_BIN_PT 0
C_MEMMAP_Z1_DEPTH 1024
C_MEMMAP_B1 0x1E000
C_MEMMAP_B1_N_BITS 32
C_MEMMAP_B1_BIN_PT 0
C_MEMMAP_B1_DEPTH 1024
C_MEMMAP_A1 0x1F000
C_MEMMAP_A1_N_BITS 32
C_MEMMAP_A1_BIN_PT 0
C_MEMMAP_A1_DEPTH 1024
C_MEMMAP_PB2MB 0x20000
C_MEMMAP_PB2MB_N_BITS 32
C_MEMMAP_PB2MB_BIN_PT 0
C_MEMMAP_PB2MB_DEPTH 512
C_MEMMAP_P1 0x00000
C_MEMMAP_P1_N_BITS 18
C_MEMMAP_P1_BIN_PT 0
C_MEMMAP_P1_DEPTH 4096
C_MEMMAP_P0 0x04000
C_MEMMAP_P0_N_BITS 18
C_MEMMAP_P0_BIN_PT 0
C_MEMMAP_P0_DEPTH 4096
C_MEMMAP_MB2PB 0x20800
C_MEMMAP_MB2PB_N_BITS 32
C_MEMMAP_MB2PB_BIN_PT 0
C_MEMMAP_MB2PB_DEPTH 512
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


bce_fp11_1x8_0_axiw_1


IP Specs
Core Version
bce_fp11_1x8_0_axiw 1.10.a


bce_fp11_1x8_0_axiw_1 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 axi_aclk I 1 clk_100_0000MHz
1 sysgen_clk I 1 clk_100_0000MHz
2 btn4b I 1 net_gnd
3 dip4b I 1 net_gnd
4 gpi8b I 1 net_gnd
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_mb_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x78800000
C_HIGHADDR 0x788FFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ID_WIDTH 1
C_S_AXI_SUPPORT_BURST 0
C_MEMMAP_Z8 0x08000
C_MEMMAP_Z8_N_BITS 32
C_MEMMAP_Z8_BIN_PT 0
C_MEMMAP_Z8_DEPTH 1024
C_MEMMAP_B8 0x09000
C_MEMMAP_B8_N_BITS 32
C_MEMMAP_B8_BIN_PT 0
C_MEMMAP_B8_DEPTH 1024
C_MEMMAP_A8 0x0A000
C_MEMMAP_A8_N_BITS 32
C_MEMMAP_A8_BIN_PT 0
C_MEMMAP_A8_DEPTH 1024
C_MEMMAP_Z7 0x0B000
C_MEMMAP_Z7_N_BITS 32
C_MEMMAP_Z7_BIN_PT 0
C_MEMMAP_Z7_DEPTH 1024
C_MEMMAP_B7 0x0C000
C_MEMMAP_B7_N_BITS 32
C_MEMMAP_B7_BIN_PT 0
C_MEMMAP_B7_DEPTH 1024
C_MEMMAP_A7 0x0D000
C_MEMMAP_A7_N_BITS 32
C_MEMMAP_A7_BIN_PT 0
C_MEMMAP_A7_DEPTH 1024
C_MEMMAP_Z6 0x0E000
C_MEMMAP_Z6_N_BITS 32
C_MEMMAP_Z6_BIN_PT 0
C_MEMMAP_Z6_DEPTH 1024
C_MEMMAP_B6 0x0F000
C_MEMMAP_B6_N_BITS 32
C_MEMMAP_B6_BIN_PT 0
C_MEMMAP_B6_DEPTH 1024
C_MEMMAP_A6 0x10000
C_MEMMAP_A6_N_BITS 32
C_MEMMAP_A6_BIN_PT 0
C_MEMMAP_A6_DEPTH 1024
C_MEMMAP_Z5 0x11000
C_MEMMAP_Z5_N_BITS 32
C_MEMMAP_Z5_BIN_PT 0
C_MEMMAP_Z5_DEPTH 1024
C_MEMMAP_B5 0x12000
C_MEMMAP_B5_N_BITS 32
C_MEMMAP_B5_BIN_PT 0
C_MEMMAP_B5_DEPTH 1024
C_MEMMAP_A5 0x13000
C_MEMMAP_A5_N_BITS 32
C_MEMMAP_A5_BIN_PT 0
C_MEMMAP_A5_DEPTH 1024
C_MEMMAP_Z4 0x14000
C_MEMMAP_Z4_N_BITS 32
C_MEMMAP_Z4_BIN_PT 0
C_MEMMAP_Z4_DEPTH 1024
C_MEMMAP_B4 0x15000
 
Name Value
C_MEMMAP_B4_N_BITS 32
C_MEMMAP_B4_BIN_PT 0
C_MEMMAP_B4_DEPTH 1024
C_MEMMAP_A4 0x16000
C_MEMMAP_A4_N_BITS 32
C_MEMMAP_A4_BIN_PT 0
C_MEMMAP_A4_DEPTH 1024
C_MEMMAP_Z3 0x17000
C_MEMMAP_Z3_N_BITS 32
C_MEMMAP_Z3_BIN_PT 0
C_MEMMAP_Z3_DEPTH 1024
C_MEMMAP_B3 0x18000
C_MEMMAP_B3_N_BITS 32
C_MEMMAP_B3_BIN_PT 0
C_MEMMAP_B3_DEPTH 1024
C_MEMMAP_A3 0x19000
C_MEMMAP_A3_N_BITS 32
C_MEMMAP_A3_BIN_PT 0
C_MEMMAP_A3_DEPTH 1024
C_MEMMAP_Z2 0x1A000
C_MEMMAP_Z2_N_BITS 32
C_MEMMAP_Z2_BIN_PT 0
C_MEMMAP_Z2_DEPTH 1024
C_MEMMAP_B2 0x1B000
C_MEMMAP_B2_N_BITS 32
C_MEMMAP_B2_BIN_PT 0
C_MEMMAP_B2_DEPTH 1024
C_MEMMAP_A2 0x1C000
C_MEMMAP_A2_N_BITS 32
C_MEMMAP_A2_BIN_PT 0
C_MEMMAP_A2_DEPTH 1024
C_MEMMAP_Z1 0x1D000
C_MEMMAP_Z1_N_BITS 32
C_MEMMAP_Z1_BIN_PT 0
C_MEMMAP_Z1_DEPTH 1024
C_MEMMAP_B1 0x1E000
C_MEMMAP_B1_N_BITS 32
C_MEMMAP_B1_BIN_PT 0
C_MEMMAP_B1_DEPTH 1024
C_MEMMAP_A1 0x1F000
C_MEMMAP_A1_N_BITS 32
C_MEMMAP_A1_BIN_PT 0
C_MEMMAP_A1_DEPTH 1024
C_MEMMAP_PB2MB 0x20000
C_MEMMAP_PB2MB_N_BITS 32
C_MEMMAP_PB2MB_BIN_PT 0
C_MEMMAP_PB2MB_DEPTH 512
C_MEMMAP_P1 0x00000
C_MEMMAP_P1_N_BITS 18
C_MEMMAP_P1_BIN_PT 0
C_MEMMAP_P1_DEPTH 4096
C_MEMMAP_P0 0x04000
C_MEMMAP_P0_N_BITS 18
C_MEMMAP_P0_BIN_PT 0
C_MEMMAP_P0_DEPTH 4096
C_MEMMAP_MB2PB 0x20800
C_MEMMAP_MB2PB_N_BITS 32
C_MEMMAP_MB2PB_BIN_PT 0
C_MEMMAP_MB2PB_DEPTH 512
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


bce_fp11_1x8_0_axiw_2


IP Specs
Core Version
bce_fp11_1x8_0_axiw 1.10.a


bce_fp11_1x8_0_axiw_2 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 axi_aclk I 1 clk_100_0000MHz
1 sysgen_clk I 1 clk_100_0000MHz
2 btn4b I 1 net_gnd
3 dip4b I 1 net_gnd
4 gpi8b I 1 net_gnd
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_mb_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x78900000
C_HIGHADDR 0x789FFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ID_WIDTH 1
C_S_AXI_SUPPORT_BURST 0
C_MEMMAP_Z8 0x08000
C_MEMMAP_Z8_N_BITS 32
C_MEMMAP_Z8_BIN_PT 0
C_MEMMAP_Z8_DEPTH 1024
C_MEMMAP_B8 0x09000
C_MEMMAP_B8_N_BITS 32
C_MEMMAP_B8_BIN_PT 0
C_MEMMAP_B8_DEPTH 1024
C_MEMMAP_A8 0x0A000
C_MEMMAP_A8_N_BITS 32
C_MEMMAP_A8_BIN_PT 0
C_MEMMAP_A8_DEPTH 1024
C_MEMMAP_Z7 0x0B000
C_MEMMAP_Z7_N_BITS 32
C_MEMMAP_Z7_BIN_PT 0
C_MEMMAP_Z7_DEPTH 1024
C_MEMMAP_B7 0x0C000
C_MEMMAP_B7_N_BITS 32
C_MEMMAP_B7_BIN_PT 0
C_MEMMAP_B7_DEPTH 1024
C_MEMMAP_A7 0x0D000
C_MEMMAP_A7_N_BITS 32
C_MEMMAP_A7_BIN_PT 0
C_MEMMAP_A7_DEPTH 1024
C_MEMMAP_Z6 0x0E000
C_MEMMAP_Z6_N_BITS 32
C_MEMMAP_Z6_BIN_PT 0
C_MEMMAP_Z6_DEPTH 1024
C_MEMMAP_B6 0x0F000
C_MEMMAP_B6_N_BITS 32
C_MEMMAP_B6_BIN_PT 0
C_MEMMAP_B6_DEPTH 1024
C_MEMMAP_A6 0x10000
C_MEMMAP_A6_N_BITS 32
C_MEMMAP_A6_BIN_PT 0
C_MEMMAP_A6_DEPTH 1024
C_MEMMAP_Z5 0x11000
C_MEMMAP_Z5_N_BITS 32
C_MEMMAP_Z5_BIN_PT 0
C_MEMMAP_Z5_DEPTH 1024
C_MEMMAP_B5 0x12000
C_MEMMAP_B5_N_BITS 32
C_MEMMAP_B5_BIN_PT 0
C_MEMMAP_B5_DEPTH 1024
C_MEMMAP_A5 0x13000
C_MEMMAP_A5_N_BITS 32
C_MEMMAP_A5_BIN_PT 0
C_MEMMAP_A5_DEPTH 1024
C_MEMMAP_Z4 0x14000
C_MEMMAP_Z4_N_BITS 32
C_MEMMAP_Z4_BIN_PT 0
C_MEMMAP_Z4_DEPTH 1024
C_MEMMAP_B4 0x15000
 
Name Value
C_MEMMAP_B4_N_BITS 32
C_MEMMAP_B4_BIN_PT 0
C_MEMMAP_B4_DEPTH 1024
C_MEMMAP_A4 0x16000
C_MEMMAP_A4_N_BITS 32
C_MEMMAP_A4_BIN_PT 0
C_MEMMAP_A4_DEPTH 1024
C_MEMMAP_Z3 0x17000
C_MEMMAP_Z3_N_BITS 32
C_MEMMAP_Z3_BIN_PT 0
C_MEMMAP_Z3_DEPTH 1024
C_MEMMAP_B3 0x18000
C_MEMMAP_B3_N_BITS 32
C_MEMMAP_B3_BIN_PT 0
C_MEMMAP_B3_DEPTH 1024
C_MEMMAP_A3 0x19000
C_MEMMAP_A3_N_BITS 32
C_MEMMAP_A3_BIN_PT 0
C_MEMMAP_A3_DEPTH 1024
C_MEMMAP_Z2 0x1A000
C_MEMMAP_Z2_N_BITS 32
C_MEMMAP_Z2_BIN_PT 0
C_MEMMAP_Z2_DEPTH 1024
C_MEMMAP_B2 0x1B000
C_MEMMAP_B2_N_BITS 32
C_MEMMAP_B2_BIN_PT 0
C_MEMMAP_B2_DEPTH 1024
C_MEMMAP_A2 0x1C000
C_MEMMAP_A2_N_BITS 32
C_MEMMAP_A2_BIN_PT 0
C_MEMMAP_A2_DEPTH 1024
C_MEMMAP_Z1 0x1D000
C_MEMMAP_Z1_N_BITS 32
C_MEMMAP_Z1_BIN_PT 0
C_MEMMAP_Z1_DEPTH 1024
C_MEMMAP_B1 0x1E000
C_MEMMAP_B1_N_BITS 32
C_MEMMAP_B1_BIN_PT 0
C_MEMMAP_B1_DEPTH 1024
C_MEMMAP_A1 0x1F000
C_MEMMAP_A1_N_BITS 32
C_MEMMAP_A1_BIN_PT 0
C_MEMMAP_A1_DEPTH 1024
C_MEMMAP_PB2MB 0x20000
C_MEMMAP_PB2MB_N_BITS 32
C_MEMMAP_PB2MB_BIN_PT 0
C_MEMMAP_PB2MB_DEPTH 512
C_MEMMAP_P1 0x00000
C_MEMMAP_P1_N_BITS 18
C_MEMMAP_P1_BIN_PT 0
C_MEMMAP_P1_DEPTH 4096
C_MEMMAP_P0 0x04000
C_MEMMAP_P0_N_BITS 18
C_MEMMAP_P0_BIN_PT 0
C_MEMMAP_P0_DEPTH 4096
C_MEMMAP_MB2PB 0x20800
C_MEMMAP_MB2PB_N_BITS 32
C_MEMMAP_MB2PB_BIN_PT 0
C_MEMMAP_MB2PB_DEPTH 512
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


bce_fp11_1x8_0_axiw_3


IP Specs
Core Version
bce_fp11_1x8_0_axiw 1.10.a


bce_fp11_1x8_0_axiw_3 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 axi_aclk I 1 clk_100_0000MHz
1 sysgen_clk I 1 clk_100_0000MHz
2 btn4b I 1 net_gnd
3 dip4b I 1 net_gnd
4 gpi8b I 1 net_gnd
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_mb_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x78A00000
C_HIGHADDR 0x78AFFFFF
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ID_WIDTH 1
C_S_AXI_SUPPORT_BURST 0
C_MEMMAP_Z8 0x08000
C_MEMMAP_Z8_N_BITS 32
C_MEMMAP_Z8_BIN_PT 0
C_MEMMAP_Z8_DEPTH 1024
C_MEMMAP_B8 0x09000
C_MEMMAP_B8_N_BITS 32
C_MEMMAP_B8_BIN_PT 0
C_MEMMAP_B8_DEPTH 1024
C_MEMMAP_A8 0x0A000
C_MEMMAP_A8_N_BITS 32
C_MEMMAP_A8_BIN_PT 0
C_MEMMAP_A8_DEPTH 1024
C_MEMMAP_Z7 0x0B000
C_MEMMAP_Z7_N_BITS 32
C_MEMMAP_Z7_BIN_PT 0
C_MEMMAP_Z7_DEPTH 1024
C_MEMMAP_B7 0x0C000
C_MEMMAP_B7_N_BITS 32
C_MEMMAP_B7_BIN_PT 0
C_MEMMAP_B7_DEPTH 1024
C_MEMMAP_A7 0x0D000
C_MEMMAP_A7_N_BITS 32
C_MEMMAP_A7_BIN_PT 0
C_MEMMAP_A7_DEPTH 1024
C_MEMMAP_Z6 0x0E000
C_MEMMAP_Z6_N_BITS 32
C_MEMMAP_Z6_BIN_PT 0
C_MEMMAP_Z6_DEPTH 1024
C_MEMMAP_B6 0x0F000
C_MEMMAP_B6_N_BITS 32
C_MEMMAP_B6_BIN_PT 0
C_MEMMAP_B6_DEPTH 1024
C_MEMMAP_A6 0x10000
C_MEMMAP_A6_N_BITS 32
C_MEMMAP_A6_BIN_PT 0
C_MEMMAP_A6_DEPTH 1024
C_MEMMAP_Z5 0x11000
C_MEMMAP_Z5_N_BITS 32
C_MEMMAP_Z5_BIN_PT 0
C_MEMMAP_Z5_DEPTH 1024
C_MEMMAP_B5 0x12000
C_MEMMAP_B5_N_BITS 32
C_MEMMAP_B5_BIN_PT 0
C_MEMMAP_B5_DEPTH 1024
C_MEMMAP_A5 0x13000
C_MEMMAP_A5_N_BITS 32
C_MEMMAP_A5_BIN_PT 0
C_MEMMAP_A5_DEPTH 1024
C_MEMMAP_Z4 0x14000
C_MEMMAP_Z4_N_BITS 32
C_MEMMAP_Z4_BIN_PT 0
C_MEMMAP_Z4_DEPTH 1024
C_MEMMAP_B4 0x15000
 
Name Value
C_MEMMAP_B4_N_BITS 32
C_MEMMAP_B4_BIN_PT 0
C_MEMMAP_B4_DEPTH 1024
C_MEMMAP_A4 0x16000
C_MEMMAP_A4_N_BITS 32
C_MEMMAP_A4_BIN_PT 0
C_MEMMAP_A4_DEPTH 1024
C_MEMMAP_Z3 0x17000
C_MEMMAP_Z3_N_BITS 32
C_MEMMAP_Z3_BIN_PT 0
C_MEMMAP_Z3_DEPTH 1024
C_MEMMAP_B3 0x18000
C_MEMMAP_B3_N_BITS 32
C_MEMMAP_B3_BIN_PT 0
C_MEMMAP_B3_DEPTH 1024
C_MEMMAP_A3 0x19000
C_MEMMAP_A3_N_BITS 32
C_MEMMAP_A3_BIN_PT 0
C_MEMMAP_A3_DEPTH 1024
C_MEMMAP_Z2 0x1A000
C_MEMMAP_Z2_N_BITS 32
C_MEMMAP_Z2_BIN_PT 0
C_MEMMAP_Z2_DEPTH 1024
C_MEMMAP_B2 0x1B000
C_MEMMAP_B2_N_BITS 32
C_MEMMAP_B2_BIN_PT 0
C_MEMMAP_B2_DEPTH 1024
C_MEMMAP_A2 0x1C000
C_MEMMAP_A2_N_BITS 32
C_MEMMAP_A2_BIN_PT 0
C_MEMMAP_A2_DEPTH 1024
C_MEMMAP_Z1 0x1D000
C_MEMMAP_Z1_N_BITS 32
C_MEMMAP_Z1_BIN_PT 0
C_MEMMAP_Z1_DEPTH 1024
C_MEMMAP_B1 0x1E000
C_MEMMAP_B1_N_BITS 32
C_MEMMAP_B1_BIN_PT 0
C_MEMMAP_B1_DEPTH 1024
C_MEMMAP_A1 0x1F000
C_MEMMAP_A1_N_BITS 32
C_MEMMAP_A1_BIN_PT 0
C_MEMMAP_A1_DEPTH 1024
C_MEMMAP_PB2MB 0x20000
C_MEMMAP_PB2MB_N_BITS 32
C_MEMMAP_PB2MB_BIN_PT 0
C_MEMMAP_PB2MB_DEPTH 512
C_MEMMAP_P1 0x00000
C_MEMMAP_P1_N_BITS 18
C_MEMMAP_P1_BIN_PT 0
C_MEMMAP_P1_DEPTH 4096
C_MEMMAP_P0 0x04000
C_MEMMAP_P0_N_BITS 18
C_MEMMAP_P0_BIN_PT 0
C_MEMMAP_P0_DEPTH 4096
C_MEMMAP_MB2PB 0x20800
C_MEMMAP_MB2PB_N_BITS 32
C_MEMMAP_MB2PB_BIN_PT 0
C_MEMMAP_MB2PB_DEPTH 512
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


irq_gen_0   IRQ_GEN


IP Specs
Core Version
irq_gen 1.00.a


irq_gen_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 S_AXI_ACLK I 1 clk_100_0000MHz
1 IRQ O 1 irq_gen_0_IRQ
2 VIO_IRQ_TICK I 1 chipscope_vio_0_sync_out
3 vio_rise_edge O 1 vio_rise_edge
4 slv_reg O 1 slv_reg
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
S_AXI SLAVE AXI axi4lite_mb_0 9 Peripherals.


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_S_AXI_DATA_WIDTH 32
C_S_AXI_ADDR_WIDTH 32
C_S_AXI_MIN_SIZE 0x000001FF
C_USE_WSTRB 0
C_DPHASE_TIMEOUT 8
C_BASEADDR 0x50000000
C_HIGHADDR 0x5000FFFF
 
Name Value
C_FAMILY virtex6
C_NUM_REG 1
C_NUM_MEM 1
C_SLV_AWIDTH 32
C_SLV_DWIDTH 32
C_S_AXI_PROTOCOL AXI4LITE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




IP TOC

chipscope_icon_0   Chipscope Integrated Controller
'The Chipscope ICON core provides a communication path between the FPGA Boundary Scan port and the other Chipscope Cores OPB IBA, PLB IBA, VIO, and the ILA.'

IP Specs
Core Version
chipscope_icon 1.06.a


chipscope_icon_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 control0 O 1 chipscope_vio_0_icon_control
1 control1 O 1 chipscope_ila_0_icon_control


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_DEVICE xc5vlx50
C_PACKAGE ffg676
C_SPEEDGRADE -11
C_NUM_CONTROL_PORTS 2
C_SYSTEM_CONTAINS_MDM 0
C_FORCE_BSCAN_USER_PORT 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


chipscope_ila_0   Chipscope Integrated Logic Analyzer (ILA)
The Chipscope Integrated Logic Analyzer (ILA) core is used to monitor internal FPGA signals in real time.

IP Specs
Core Version
chipscope_ila 1.05.a


chipscope_ila_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 chipscope_ila_control I 1 chipscope_ila_0_icon_control
1 CLK I 1 clk_100_0000MHz
2 TRIG0 I 1 vio_rise_edge & slv_reg & irq_gen_0_IRQ & chipscope_vio_0_sync_out


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_DEVICE xc5vlx50
C_PACKAGE ffg676
C_SPEEDGRADE -11
C_NUM_DATA_SAMPLES 4096
C_DATA_SAME_AS_TRIGGER 1
C_DATA_IN_WIDTH 32
C_ENABLE_TRIGGER_OUT 1
C_DISABLE_RPM 0
C_RISING_CLOCK_EDGE 1
C_MAX_SEQUENCER_LEVELS 1
C_ENABLE_STORAGE_QUALIFICATION 1
C_TRIG0_UNITS 1
C_TRIG0_TRIGGER_IN_WIDTH 4
C_TRIG0_UNIT_COUNTER_WIDTH 0
C_TRIG0_UNIT_MATCH_TYPE basic
C_TRIG1_UNITS 0
C_TRIG1_TRIGGER_IN_WIDTH 8
C_TRIG1_UNIT_COUNTER_WIDTH 0
C_TRIG1_UNIT_MATCH_TYPE basic
C_TRIG2_UNITS 0
C_TRIG2_TRIGGER_IN_WIDTH 8
C_TRIG2_UNIT_COUNTER_WIDTH 0
C_TRIG2_UNIT_MATCH_TYPE basic
C_TRIG3_UNITS 0
C_TRIG3_TRIGGER_IN_WIDTH 8
C_TRIG3_UNIT_COUNTER_WIDTH 0
C_TRIG3_UNIT_MATCH_TYPE basic
C_TRIG4_UNITS 0
C_TRIG4_TRIGGER_IN_WIDTH 8
C_TRIG4_UNIT_COUNTER_WIDTH 0
C_TRIG4_UNIT_MATCH_TYPE basic
C_TRIG5_UNITS 0
C_TRIG5_TRIGGER_IN_WIDTH 8
C_TRIG5_UNIT_COUNTER_WIDTH 0
C_TRIG5_UNIT_MATCH_TYPE basic
C_TRIG6_UNITS 0
C_TRIG6_TRIGGER_IN_WIDTH 8
 
Name Value
C_TRIG6_UNIT_COUNTER_WIDTH 0
C_TRIG6_UNIT_MATCH_TYPE basic
C_TRIG7_UNITS 0
C_TRIG7_TRIGGER_IN_WIDTH 8
C_TRIG7_UNIT_COUNTER_WIDTH 0
C_TRIG7_UNIT_MATCH_TYPE basic
C_TRIG8_UNITS 0
C_TRIG8_TRIGGER_IN_WIDTH 8
C_TRIG8_UNIT_COUNTER_WIDTH 0
C_TRIG8_UNIT_MATCH_TYPE basic
C_TRIG9_UNITS 0
C_TRIG9_TRIGGER_IN_WIDTH 8
C_TRIG9_UNIT_COUNTER_WIDTH 0
C_TRIG9_UNIT_MATCH_TYPE basic
C_TRIG10_UNITS 0
C_TRIG10_TRIGGER_IN_WIDTH 8
C_TRIG10_UNIT_COUNTER_WIDTH 0
C_TRIG10_UNIT_MATCH_TYPE basic
C_TRIG11_UNITS 0
C_TRIG11_TRIGGER_IN_WIDTH 8
C_TRIG11_UNIT_COUNTER_WIDTH 0
C_TRIG11_UNIT_MATCH_TYPE basic
C_TRIG12_UNITS 0
C_TRIG12_TRIGGER_IN_WIDTH 8
C_TRIG12_UNIT_COUNTER_WIDTH 0
C_TRIG12_UNIT_MATCH_TYPE basic
C_TRIG13_UNITS 0
C_TRIG13_TRIGGER_IN_WIDTH 8
C_TRIG13_UNIT_COUNTER_WIDTH 0
C_TRIG13_UNIT_MATCH_TYPE basic
C_TRIG14_UNITS 0
C_TRIG14_TRIGGER_IN_WIDTH 8
C_TRIG14_UNIT_COUNTER_WIDTH 0
C_TRIG14_UNIT_MATCH_TYPE basic
C_TRIG15_UNITS 0
C_TRIG15_TRIGGER_IN_WIDTH 8
C_TRIG15_UNIT_COUNTER_WIDTH 0
C_TRIG15_UNIT_MATCH_TYPE basic
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


chipscope_vio_0   Chipscope Virtual IO (VIO)
Chipscope VIO (Virtual IO) core both monitors and drives internal FPGA signals in real time.

IP Specs
Core Version
chipscope_vio 1.05.a


chipscope_vio_0 IP Image
PORT LIST
These are the ports listed in the MHS file.
# NAME DIR [LSB:MSB] SIGNAL
0 chipscope_icon_control I 1 chipscope_vio_0_icon_control
1 clk I 1 clk_100_0000MHz
2 sync_out O 1 chipscope_vio_0_sync_out


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex2
C_DEVICE xc4vfx12
C_PACKAGE ff1016
C_SPEEDGRADE -11
C_ASYNC_INPUT_ENABLE 0
C_ASYNC_INPUT_WIDTH 8
C_ASYNC_OUTPUT_ENABLE 0
 
Name Value
C_ASYNC_OUTPUT_WIDTH 8
C_SYNC_INPUT_ENABLE 0
C_SYNC_INPUT_WIDTH 8
C_SYNC_OUTPUT_ENABLE 1
C_SYNC_OUTPUT_WIDTH 1
C_RISING_CLOCK_EDGE 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


clock_generator_0   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 4.03.a IP


clock_generator_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 LOCKED O 1 proc_sys_reset_0_Dcm_locked
1 CLKOUT0 O 1 clk_100_0000MHz
2 RST I 1 RESET
3 CLKIN I 1 CLK


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_DEVICE NOT_SET
C_PACKAGE NOT_SET
C_SPEEDGRADE NOT_SET
C_CLKIN_FREQ 200000000
C_CLKOUT0_FREQ 100000000
C_CLKOUT0_PHASE 0
C_CLKOUT0_GROUP NONE
C_CLKOUT0_BUF TRUE
C_CLKOUT0_VARIABLE_PHASE FALSE
C_CLKOUT1_FREQ 0
C_CLKOUT1_PHASE 0
C_CLKOUT1_GROUP NONE
C_CLKOUT1_BUF TRUE
C_CLKOUT1_VARIABLE_PHASE FALSE
C_CLKOUT2_FREQ 0
C_CLKOUT2_PHASE 0
C_CLKOUT2_GROUP NONE
C_CLKOUT2_BUF TRUE
C_CLKOUT2_VARIABLE_PHASE FALSE
C_CLKOUT3_FREQ 0
C_CLKOUT3_PHASE 0
C_CLKOUT3_GROUP NONE
C_CLKOUT3_BUF TRUE
C_CLKOUT3_VARIABLE_PHASE FALSE
C_CLKOUT4_FREQ 0
C_CLKOUT4_PHASE 0
C_CLKOUT4_GROUP NONE
C_CLKOUT4_BUF TRUE
C_CLKOUT4_VARIABLE_PHASE FALSE
C_CLKOUT5_FREQ 0
C_CLKOUT5_PHASE 0
C_CLKOUT5_GROUP NONE
C_CLKOUT5_BUF TRUE
C_CLKOUT5_VARIABLE_PHASE FALSE
C_CLKOUT6_FREQ 0
C_CLKOUT6_PHASE 0
C_CLKOUT6_GROUP NONE
C_CLKOUT6_BUF TRUE
C_CLKOUT6_VARIABLE_PHASE FALSE
C_CLKOUT7_FREQ 0
C_CLKOUT7_PHASE 0
C_CLKOUT7_GROUP NONE
C_CLKOUT7_BUF TRUE
C_CLKOUT7_VARIABLE_PHASE FALSE
C_CLKOUT8_FREQ 0
C_CLKOUT8_PHASE 0
C_CLKOUT8_GROUP NONE
C_CLKOUT8_BUF TRUE
C_CLKOUT8_VARIABLE_PHASE FALSE
C_CLKOUT9_FREQ 0
C_CLKOUT9_PHASE 0
C_CLKOUT9_GROUP NONE
C_CLKOUT9_BUF TRUE
C_CLKOUT9_VARIABLE_PHASE FALSE
C_CLKOUT10_FREQ 0
 
Name Value
C_CLKOUT10_PHASE 0
C_CLKOUT10_GROUP NONE
C_CLKOUT10_BUF TRUE
C_CLKOUT10_VARIABLE_PHASE FALSE
C_CLKOUT11_FREQ 0
C_CLKOUT11_PHASE 0
C_CLKOUT11_GROUP NONE
C_CLKOUT11_BUF TRUE
C_CLKOUT11_VARIABLE_PHASE FALSE
C_CLKOUT12_FREQ 0
C_CLKOUT12_PHASE 0
C_CLKOUT12_GROUP NONE
C_CLKOUT12_BUF TRUE
C_CLKOUT12_VARIABLE_PHASE FALSE
C_CLKOUT13_FREQ 0
C_CLKOUT13_PHASE 0
C_CLKOUT13_GROUP NONE
C_CLKOUT13_BUF TRUE
C_CLKOUT13_VARIABLE_PHASE FALSE
C_CLKOUT14_FREQ 0
C_CLKOUT14_PHASE 0
C_CLKOUT14_GROUP NONE
C_CLKOUT14_BUF TRUE
C_CLKOUT14_VARIABLE_PHASE FALSE
C_CLKOUT15_FREQ 0
C_CLKOUT15_PHASE 0
C_CLKOUT15_GROUP NONE
C_CLKOUT15_BUF TRUE
C_CLKOUT15_VARIABLE_PHASE FALSE
C_CLKFBIN_FREQ 0
C_CLKFBIN_DESKEW NONE
C_CLKFBOUT_FREQ 0
C_CLKFBOUT_PHASE 0
C_CLKFBOUT_GROUP NONE
C_CLKFBOUT_BUF TRUE
C_PSDONE_GROUP NONE
C_EXT_RESET_HIGH 1
C_CLK_PRIMITIVE_FEEDBACK_BUF FALSE
C_CLKOUT0_DUTY_CYCLE 0.500000
C_CLKOUT1_DUTY_CYCLE 0.500000
C_CLKOUT2_DUTY_CYCLE 0.500000
C_CLKOUT3_DUTY_CYCLE 0.500000
C_CLKOUT4_DUTY_CYCLE 0.500000
C_CLKOUT5_DUTY_CYCLE 0.500000
C_CLKOUT6_DUTY_CYCLE 0.500000
C_CLKOUT7_DUTY_CYCLE 0.500000
C_CLKOUT8_DUTY_CYCLE 0.500000
C_CLKOUT9_DUTY_CYCLE 0.500000
C_CLKOUT10_DUTY_CYCLE 0.500000
C_CLKOUT11_DUTY_CYCLE 0.500000
C_CLKOUT12_DUTY_CYCLE 0.500000
C_CLKOUT13_DUTY_CYCLE 0.500000
C_CLKOUT14_DUTY_CYCLE 0.500000
C_CLKOUT15_DUTY_CYCLE 0.500000
C_CLK_GEN UPDATE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


proc_sys_reset_0   Processor System Reset Module
Reset management module

IP Specs
Core Version Documentation
proc_sys_reset 3.00.a IP


proc_sys_reset_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MB_Debug_Sys_Rst I 1 proc_sys_reset_0_MB_Debug_Sys_Rst
1 Dcm_locked I 1 proc_sys_reset_0_Dcm_locked
2 MB_Reset O 1 proc_sys_reset_0_MB_Reset
3 Slowest_sync_clk I 1 clk_100_0000MHz
4 Interconnect_aresetn O 1 proc_sys_reset_0_Interconnect_aresetn
5 Ext_Reset_In I 1 RESET
6 Aux_Reset_In I 1 gpio_rstn


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SUBFAMILY lx
C_EXT_RST_WIDTH 4
C_AUX_RST_WIDTH 4
C_EXT_RESET_HIGH 1
C_AUX_RESET_HIGH 0
C_NUM_BUS_RST 1
C_NUM_PERP_RST 1
C_NUM_INTERCONNECT_ARESETN 1
C_NUM_PERP_ARESETN 1
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


util_bus_split_0   Utility Bus Split
Bus splitting primitive

IP Specs
Core Version Documentation
util_bus_split 1.00.a IP


util_bus_split_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Out2 O 1 gpio_rstn
1 Sig I 1 psGpio_o


Parameters
These are the current parameter settings for this module.

Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SIZE_IN 64
C_LEFT_POS 0
C_SPLIT 63
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOC


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.