Adaptive Noise Canceller LS Lattice Demo


This adaptive noise canceller (ANC) demo presents the use of our least-square lattice (LSL) IP core. The LS lattice adaptive filter employed within the core is implemented as four-stage pipelined unit. The core operates on 16-bit two's complement integer (fixed-point) input/output data. However, the LS lattice algorithm and all other calculations are implemented in the 19-bit logarithmic number system (LNS) arithmetic. Conversions from integer to LNS representation and vice versa are integrated within the LS lattice core.

The ANC LSL demo contained in this package has been prepared for testing on two different prototyping boards:

  1. The Celoxica RC200(E) board equipped with the Xilinx Virtex-II XC2V1000-4 FPGA.
  2. The XESS XSV-800 board equipped with the Xilinx Virtex XCV800-4 FPGA.

Package Summary

Title Adaptive Noise Canceller Demo based on the LS Lattice Filter
Short title ANC LSL Demo
Authors Z. Pohl, J. Kadlec, M. Tichy
License Freeware license
See the ‘license.txt’ file in the package.
Size 29275337 Bytes
Required tools
& platform
Celoxica RC200(E) board
Board support package (FTU2)
XESS XSV-800 board and XESS Tools
Installation notes Read documentation contained in the package
and follow instructions in the ‘anclsl_demo.pdf’ file.

Result Category

Project number Contract section Year RIV category Comment
1M0567 VS1 2008 S Functional sample (demo)

Contact Person

Please, do not hesitate to contact Zdenek Pohl to obtain more information.