RECONF 2
The aim of the RECONF 2 project is to develop a design environment suitable for an efficient use of the dynamically reconfigurable FPGA. This new type of FPGA will make it possible to design innovative low cost architectures. That will open new application opportunities, such as implementation of adaptive computing systems.
The main targeted application domains are real time image processing, signal processing. These applications are included in most embedded systems found in aeronautic, automation, multimedia, industrial process control. Although the environment will be usable by all Real Time embedded systems manufacturers, it will represent a unique opportunity for SMEs to access this cutting-edge technology and to develop complex, high performance applications at low costs.
Please follow links below for more information:
Project presentation
Project has been presented during 16th IFAC World Congress in Prague, July 4 - 8,2005, at UTIA & IDEALIST booth.
Press Release in the Czech Language
More information about the Reconf 2 project is provided in this official press release document in the Czech language.
Press Release
More information about the Reconf 2 project is provided in this official press release. Please, don't hesitate to contact Jiri Kadlec to obtain more information.
| Acronym: | RECONF 2 |
| Name: | Design methodology and environment for dynamic RECONFigurable FPGA |
| Project No.: | IST-2001-34016 |
| web: | https://cordis.europa.eu/project/id/IST-2001-34016 |
| Call: | IST-01-7-1A |
| Consortium: | MBDA France (coordinator) Atmel Nantes Sa, France Deltatec, Belgium Kayser Italia, Srl., Italy Technical University of Catalunya, Spain Institute of Information Theory and Automation of the AS CR |
| Duration: | 1 March 2002 - 31 December 2004 |
Presentations
- RECONF - Project Presentation
- MATLAB/Simulink Based Methodology for Rapid FPGA Prototyping
- FPGA Prototyping Using Extensions to MATLAB/Simulink
- Dynamic Reconfiguration for Atmel FPGAs
- Autocorrelation Demo
- FPSLIC Prototyping Board ADK1
- Design Guidelines for AT40K/AT94K Dynamic Reconfiguration
- Extended FPSLIC Platform for Dynamic Reconfiguration
- Automatic Partitioning for Dynamic Reconfiguration and Retiming
- 24-bit Floating-Point Accelerator in Atmel FPSLIC and Xilinx Virtex2
- AVR Core Supported Dynamic Reconfiguration
- Dynamic Reconfiguration of FPGAs
- FPSLIC Prototyping Board for Portable Applications ADK1
- FPSLIC IP CORES for ADK1
- Front End Tools for a Dynamic Reconfiguration
- GIN - A Note-Taker for Blind People: An Example of Using Dynamic Reconfiguration of FPGAs
- Dynamic Reconfiguration in FPGA-Based SoC Designs
- Figaro - An Automatic Tool-Flow for Designs with Dynamic Reconfiguration
- Design Methodology and Environment for Dynamically RECONFigurable FPGAs
- Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC
