News Profile Presentations Staff Contact

FitOptiVis
From the cloud to the edge - smart IntegraTion and OPtimization Technologies for highly efficient Image and VIdeo processing Systems

The objective of FitOptiVis project is to develop an integral approach for smart integration of image- and video-processing pipelines for CPS covering a reference architecture, supported by low-power, high-performance, smart devices, and by methods and tools for combined design-time and run-time multi-objective optimisation within system and environment constraints.

Low latency Image processing is often crucial for autonomy, and performing the right interaction of the CPS with its environment. The most important CPS in the project have sensors and processing at distributed places. For many reasons (parts of) CPS has to operate on low energy, whereas the complete system needs results with low latency. The focus of the project is on multi-objective optimisation for performance and energy use. However, other qualities, like reliability, security etc. also play a role in the optimisation.

Please, do not hesitate to contact Jiri Kadlec and Zdenek Pohl for more information.

Project results

• Data Movers in DTRiMC tool for TE0726 03M 07S board

• DTRiMC tool for TE0808-09-EG-ES1 module on TEBF0808 carrier board

• DTRiMC tool for TE0726-03M board

• DTRiMC tool for TE0808-15-EG-1EE module on TEBF0808 carrier board

• DTRiMC tool for TE0820-02-3CG-1E module on TE0701-06 carrier board

• DTRiMC tool for TE0820-03-4EV-1E module on TE0701-06 carrier board

• Eight FP03x8 accelerators for TE0808-09-EG-ES1 module on TEBF0808 carrier board

• FP01x8 Accelerator on TE0726-03M

• Two serial connected evaluation versions of FP03x8 accelerators for TE0820-03-4EV-1E module on TE0701-06 carrier board

• Design Time and Run Time Resources for the ZynqBerry Board TE0726-03M with SDSoC 2018.2 Support

• Design Time and Run Time Resources for Zynq Ultrascale+ TE0808-04-15EG-1EE with SDSoC 2018.2 Support

• Design Time and Run Time Resources for Zynq Ultrascale+ TE0820-03-4EV-1E with SDSoC 2018.2 Support

• Video Input/Output IP Cores for TE0820 SoM with TE0701 Carrier and and Avnet HDMI Input/Output FMC Module

• Video Input/Output IP Cores for Xilinx ZCU102 with Avnet HDMI Input/Output FMC Module

• Stereo Demo

• Live Canny Edge Detection Demo for TE0808+TEBF0808 Trenz Board

Project presentation

• Dynamic HW Reconfiguration on Xilinx ZynqMP TE0820-03-3EG-1EA module
  (presented during EW 2019 at the TRENZ Electronics company booth)

Acronym:	FitOptiVis
Title:	From the cloud to the edge - smart IntegraTion and OPtimization Technologies for highly efficient Image and VIdeo processing Systems
Project No.:	783162 (ECSEL) 8A18013 (MSMT)
Call:	H2020-ECSEL-2017-2-RIA-two-stage
web:	https://fitoptivis.eu/
Consortium:	Philips Medical Systems Netherland BV (coordinator) Futura Composites BV, Netherlands Delft University of Technology, Netherlands Eindhoven University of Technology, Netherlands CAMEA, s.r.o., Czech Rep. Charles University in Prague, Faculty of Mathematics and Physics, Czech Rep. REX Controls, s.r.o., Czech Rep. Brno University of Technology, Faculty of Information Technology, Czech Rep. University of West Bohemia, Dept. of Automatic Control, Czech Rep. Institute of Information Theory and Automation of the CAS, Czech Rep. HURJA Solutions Oy, Finland Nokia Technologies Oy, Finland Tampere University of Technology, Finland University of Turku, Finland Visidon Oy, Finland HI-IBERIA Ingenieria y Proyectos SL, Spain Instituto Tecnologico de Informatica, Spain R G B Medical Devices SA, Spain Seven Solutions SL, Spain Schneider Electric Espana SA, Spain Thales Alenia Space Espana SA, Spain University Cantabria, Spain University of Granada, Spain Abinsula, Italy Aitek S.p.A., Italy Societa Acquedotti Tirreni S.p.A., Italy ISARail S.p.A., Italy University of Cagliari, Dept. of Electrical and Electronic Engineering, Italy University of Sassari, Italy University of L'Aquila, Center of Excellence DEWS, Italy
Duration:	1 June 2018 - 30 November 2021