Cross Ambiguity function Accelerator presentation in MAPLD
Our group will present a paper and a poster at the MAPLD conference in Washington D.C., DC, USA (Sept. 26-28, 2006). The paper describes the FPGA based accelerator architecture and implementation for Cross Ambiguity function. The accelerator is planned to be used as a part of the Passive Coherent Location signal engine.
PicoBlaze Network for DSP Computations
The
March issue of the Xilinx Embedded Magazine published our article that describes the concept
of a network of master/slave PicoBlaze processors used for flexible FPGA implementations of DSP
algorithms.
More details can be found on the
Xilinx web page.
UTIA and Celoxica Sign a Research Contract on DSP
Last week UTIA and Celoxica signed a research contract under which UTIA will develop selected DSP cores for
programmable logic implementations of next-generation digital-signal processing applications.
For more information see
Celoxica press release.
A short notice was also published in
the June 12 issue of the Czech news portal idnes.cz.
UTIA booth at ARTEMIS Annual Conference
We presented our current research projects at the 3rd ARTEMIS Annual Conference held in Graz, Austria, on May 22-24, 2006, at UTIA booth.
A paper in the Czech Communication Technology Journal
The Czech Communication Technology Journal has published an article about dynamic reconfiguration of FPGAs (in Czech) jointly written by researchers from our department and the Department of Computer Science, Czech Technical University, Faculty of Electrical Engineering.
UTIA in European Electronic Engineer
An article in European Electronic Engineer mentions UTIA research on tools for dynamic reconfiguration for FPGAs.