FPL2007 Conference

Our group will present two short papers at the FPL conference in Amsterdam. The first paper will describe our flexible platform for acceleration of floating-point calculations in MicroBlaze. The second paper will describe an implementation of an RLS lattice filter with probabilistic order estimation.

Martin Danek
August 15, 2007

UTIA at EW2007

UTIA gave two invited presentations at a workshop on embedded systems in the Czech Republic, organized at the Embedded World 2007 in Nurnberg. The first talk described the embedded systems research carried out in the Czech Republic, while the second talk showed work done at UTIA in partial runtime reconfiguration of FPGAs. More details can be found at the Czech FP7 web (in Czech) or at the web of the German-Czech Chamber of Industry and Commerce (Czech or German).

Martin Danek
April 23, 2007

UTIA Stand at IST2006

Our group will present two FPGA-based demos at the PicoNet stand at the IST2006 event next week in Helsinki. The first demo will show an interactive mixed-signal oscilloscope with data capture and visualization of analog data. The oscilloscope design has been implemented in three separate FPGA configurations programmed in the Celoxica DK4 tool. The second demo will demonstrate high-throughput DSP computation in a network of PicoBlaze processors with reconfigurable hardware accelerators. More information can be found at the official IST2006 PicoNet exhibit page.
We are looking forward to meeting you there.
Visit our virtual booth.

Jiri Kadlec
November 14, 2006

2006 MAPLD International Conference

We will present Reconfigurable Handel-C FSL accelerators for MicroBlaze poster at the MAPLD 2006 conference in Washington D.C., USA (Sep. 26-28, 2006). The poster shows concept of SW reconfigurable HW accelerators with a platform independent interface.

Roman Bartosinski
Sept. 21, 2006

Cross Ambiguity function Accelerator presentation in MAPLD

Our group will present a paper and a poster at the MAPLD conference in Washington D.C., DC, USA (Sept. 26-28, 2006). The paper describes the FPGA based accelerator architecture and implementation for Cross Ambiguity function. The accelerator is planned to be used as a part of the Passive Coherent Location signal engine.

Antonin Hermanek
Sept. 20, 2006

PicoBlaze Network for DSP Computations

The  March issue of the Xilinx Embedded Magazine published our article that describes the concept of a network of master/slave PicoBlaze processors used for flexible FPGA implementations of DSP algorithms.
More details can be found on the  Xilinx web page.

Jiri Kadlec
July 10, 2006