AMWAS Workshop
Our group presented a platform for digital signal processing in FPGA-based embedded systems at the Aether-Morpheus Workshop and Summer School in Paris. The platform provides extensions to the Xilinx EDK tool that implement efficient floating-point vector operations. The platform is based on a network of heterogenous reprogrammable worker units. Each unit contains several basic floating-point operations (e.g. ADD, MUL) that can be interconnected in several ways; each such configuration implements a basic vector operation (e.g. VADD, VMAC). The software configurability and reprogrammability increases reuse of the hardware function units, and reduces the complexity of the final data path.
SoC2007 Conference
Our group will present a novel emulation technique for fault emulation in generic netlists at the SOC conference in Tampere. The technique has been developed within RETAC project.
FPL2007 Conference
Our group will present two short papers at the FPL conference in Amsterdam. The first paper will describe our flexible platform for acceleration of floating-point calculations in MicroBlaze. The second paper will describe an implementation of an RLS lattice filter with probabilistic order estimation.
UTIA at EW2007
UTIA gave two invited presentations at a workshop on embedded systems in the Czech Republic, organized at the Embedded World 2007 in Nurnberg. The first talk described the embedded systems research carried out in the Czech Republic, while the second talk showed work done at UTIA in partial runtime reconfiguration of FPGAs. More details can be found at the Czech FP7 web (in Czech) or at the web of the German-Czech Chamber of Industry and Commerce (Czech or German).
UTIA Stand at IST2006
Our group will present two FPGA-based demos at the PicoNet stand at the IST2006 event next week in Helsinki.
The first demo will show an interactive mixed-signal oscilloscope with data capture and visualization of analog data.
The oscilloscope design has been implemented in three separate FPGA configurations programmed in the
Celoxica DK4 tool. The second demo will demonstrate high-throughput DSP computation
in a network of PicoBlaze processors with reconfigurable hardware accelerators. More information
can be found at
the official IST2006 PicoNet exhibit page.
We are looking forward to meeting you there.
Visit our virtual booth.
2006 MAPLD International Conference
We will present Reconfigurable Handel-C FSL accelerators for MicroBlaze poster at the MAPLD 2006 conference in Washington D.C., USA (Sep. 26-28, 2006). The poster shows concept of SW reconfigurable HW accelerators with a platform independent interface.