FPL 2002 Presentations

The results of the HSLA project will be presented at the 12th International Conference on Field Programmable Logic and Applications (FPL 2002)in Montpelier, France. The presentation will include 1 paper, 3 posters and running demo. Follow the links for the handouts of the posters.

Lattice IP Core used in Real-time Lattice Demo on XESS Board

Logarithmic dual pipelined ALU Macros 19-bit and 32-bit

Adaptive Recursive Least Squares Lattice Filter

Presentations

• Logarithmic (dual) ALU Core
• Logaritmická (dvojitá) aritmetická jednotka
• Adaptive Recursive Least Squares Lattice Filter
• Adaptivní Lattice filtr
• Lattice IP Core used in Real-time Lattice Demo on XESS Board
• RLS Lattice Macros for Virtex/E/Virtex2 with LNS ALU 19/32-bit
• Adaptive Recursive Least Square Lattice Filter
• Logarithmic Dual Pipelined ALU Macros 19-bit and 32-bit
• Matlab Toolbox for High-Level Bit-Exact Emulation of FPGA Designs
• Pipelined Implementations of the a Priori Error-Feedback LSL Algorithm Using Logarithmic Arithmetic
• Logarithmic Arithmetic Core Based RLS Lattice Implementation
• European Logarithmic Microprocessor
• Floating-Point Like Arithmetic for FPGA