Implementation of Accelerators for Decoding Reed-Solomon and Convolution error-correcting code on FPGA
Description
The accelerators encode and decode Reed-Solomon and block convolution error-correcting code. Reed-Solomon and block convolution code are mostly used FEC on this days. Accelerators are implemented on FPGA (Altera FPGA) and accelerator for decoding of convolution code is implemented on DSP (Texas Instruments TMS320C6416) too.
Package Summary
| Title | FEC accelerators |
| Filename | FEC.zip |
| License | Freeware (See the 'license.txt' file in the package.) |
| Package content | ZIP archive with bitstreams of accelerators and additional functions for Matlab |
| Size | 7051631 Bytes |
| Required tools & platform |
Matlab R14 or newer for Windows (OS dependent), Code Composer Studio v3.1, Quartus II Development boards "Nios Development Board", Cyclone Edition"; "Nios Development Board, Stratix Edition"; "Stratix II EP2S180 DSP Development Board"; "TMS320C6416T DSK" |
| Installation notes | See the 'readme.txt' file in the package. |
Result Category
| Project number | Year | RIV category | Comment |
| 1ET300750402 1ET100750408 |
2008 | S | functional sample (demo) |