Fault Injection into Emulated ASIC Netlists Using Partial Runtime Reconfiguration of FPGA
Description
This package contains the ExtractFL tool. This tool is part of a design flow for emulation of faults in ASIC netlists using FPGAs that was developed within the RETAC project. Faults are injected into the emulated netlist using partial runtime reconfiguration. The ExtractFl tool extracts FPGA configuration data for every considered fault from placed and routed netlists for FPGA.
Package Summary
| Title |
ExtractFL tool |
| Filename |
extractfl.zip |
| License |
Freeware |
| Package content |
ZIP archive with the ExtractFL tool and an example |
| Size |
3 689 734 Bytes |
Required tools
& platform |
The ExtractFL tool is an executable file for Windows. No additional tools are required. |
Result Category
Please, do not hesitate to contact
Jiri Kadlec to obtain more information.
