GA 102/04/2137
This project is aimed at utilizing and deepening the current results achieved by the project members so as to create a synergic effect that will result in creating an integrated circuit with new qualities. The current trend in digital VLSI design is such that supply voltages decrease as well as feature sizes (which are now well under 0.1 microns) and chip sizes increase. These trends on the one hand enable to increase the computing power of the designed circuits, and at the same time to decrease the price per one transistor, but they also make the circuits more susceptible to errors, their behaviour becomes more or less stochastic. These reasons change the meaning of individual circuit parameters, it becomes acceptable to use a larger part of the circuit for service functions and it is often economically justifiable to back up function units so as to increase the reliability of the whole circuit. The EU countries have already realized that the optimal design approach to new VLSI circuits has been changing, they substantially support the development of the VLSI design and manufacturing technology, make it easier for the academic institutions and industrial companies to use new technologies and new design methods. The goal of this project is to design a new, advanced design methodology for reconfigurable circuits that will be based on the new technological possibilities and to make it accessible both to local small and medium-size enterprises and to education of students at universities.Name: | Design of Highly Reliable Control Systems Built on dynamically Reconfigurable FPGAs |
Provider: | Grant Agency of the Czech Republic |
Project No.: | GA102/04/2137 |
Consortium: | Faculty of Mechatronics, TU Liberec Faculty of Electrical Engineering, CTU in Prague Institute of Information Theory and Automation of the AS CR |
Duration: | 1.1.2004 - 31.12.2006 |
Presentations
- FPGA Modelling for High-Performance Algorithms
- AVR Core Supported Dynamic Reconfiguration
- Figaro - An Automatic Tool-Flow for Designs with Dynamic Reconfiguration
- Fault Classification for Self-Checking Circuits Implemented in FPGA
- Design and Verification Methodology for Reconfigurable Designs in Atmel FPSLIC
- Floating-Point DSP Acceleration in FPGAs: The First Step Towards the SANE Concept