CAK
Center for Applied Cybernetics (the Center) takes advantage of established research background and teams and provide concerted action of leading research groups and hi-tech companies in the country. It offers to its young researchers opportunity for creative growths and top-class working conditions for research and development in a perspective field. The Government investment will pay off in progress in the filed, increase of qualified workforce and directly through the financial growth of participating industrial companies. Our department has joined the project with the Control Systems group. The group deal with the following problems:- Distributed control systems
- Operating systems for Real-Time control
- Internet programming
- Industrial automation and Fieldbuses
- Rapid prototyping
| Acronym: | CAK |
| Name: | Centrum aplikovane kybernetiky (Centre for Applied Cybernetics) |
| Project No.: | LN00B096 |
| web: | LN00B096 |
| Consortium: | Faculty of Electrical Engineering, CTU Prague Faculty of Mechanical Engineering, CTU Prague Faculty of Electrical Engineering and Communication, BUT Brno Faculty of Applied Sciences, UWB Pilsen Institute of Information Theory and Automation of the AS CR Institute of Informatics of the AS CR CertiCon Cygni Neovision UniControls Camea |
| Duration: | July 2000 - December 2004 |
Prezentace
- Alpha Accelerator for Real Time Workshop - Windows Target
- Intellectual Property Cores Design for Programmable Logic
- IP Cores Design for Programmable Logic
- Prototyping of DSP Algorithms on FPGA
- Lattice IP Core used in Real-time Lattice Demo on XESS Board
- RLS Lattice Macros for Virtex/E/Virtex2 with LNS ALU 19/32-bit
- Matlab Toolbox for High-Level Bit-Exact Emulation of FPGA Designs
- Logarithmic Arithmetic Core Based RLS Lattice Implementation
- Floating-Point Like Arithmetic for FPGA
- RLS Lattice - Celoxica RC200 Demo
- Using Logarithmic Arithmetic for FPGA Implementation of the Givens Rotations
- MATLAB/Simulink Based Methodology for Rapid FPGA Prototyping
- FPGA Implementation of the Adaptive Lattice Filter
- Prototyping of DSP Algorithms on FPGA
- FPGA Prototyping Using Extensions to MATLAB/Simulink
- Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA
- Scalable, Short-Latency Floating-Point
- FPGA Implementation of Recursive QR Update Using LNS Arithmetic
- GIN - A Note-Taker for Blind People: An Example of Using Dynamic Reconfiguration of FPGAs
- Performance Tuning of Iterative Algorithms in Signal Processing
- Architecture Design for FPGA Implementation of Finite Interval CMA
