FPL 2004 Virtual Booth

• Scalable, Short-Latency Floating-Point (1.5 GFLOPs on Virtex XC2V1000-4) (.jpg 910 KB)
• Using logarithmic arithmetic to implement the Recursive Least Squares (QR) algorithm in FPGA (.jpg 588 KB)
• 24-Bit Floating-Point Accelerator in Atmel FPSLIC and Xilinx Virtex2 (.jpg 689 KB)
• Automatic Partitioning for Dynamic Reconfiguration and Re-timing (.jpg 675 KB)
• Extended FPSLIC Platform for Dynamic Reconfiguration (.jpg 773 KB)
• Design Guidelines for AT40K / AT94K Dynamic Reconfiguration (.jpg 873 KB)
• FPSLIC Prototyping Board ADK1 (.jpg 679 KB)
• Dynamic Reconfiguration of FPGAs (.jpg 679 KB)
• AutoCorrelation Demo (.jpg 755 KB)